132 lines
4.0 KiB
Go
132 lines
4.0 KiB
Go
![]() |
package amd64util
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import (
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"bytes"
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"encoding/binary"
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"fmt"
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"github.com/go-delve/delve/pkg/proc"
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)
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// AMD64Xstate represents amd64 XSAVE area. See Section 13.1 (and
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// following) of Intel® 64 and IA-32 Architectures Software Developer’s
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// Manual, Volume 1: Basic Architecture.
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type AMD64Xstate struct {
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AMD64PtraceFpRegs
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Xsave []byte // raw xsave area
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AvxState bool // contains AVX state
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YmmSpace [256]byte
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Avx512State bool // contains AVX512 state
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ZmmSpace [512]byte
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}
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// AMD64PtraceFpRegs tracks user_fpregs_struct in /usr/include/x86_64-linux-gnu/sys/user.h
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type AMD64PtraceFpRegs struct {
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Cwd uint16
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Swd uint16
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Ftw uint16
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Fop uint16
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Rip uint64
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Rdp uint64
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Mxcsr uint32
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MxcrMask uint32
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StSpace [32]uint32
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XmmSpace [256]byte
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Padding [24]uint32
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}
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// Decode decodes an XSAVE area to a list of name/value pairs of registers.
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func (xsave *AMD64Xstate) Decode() []proc.Register {
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var regs []proc.Register
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// x87 registers
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regs = proc.AppendUint64Register(regs, "CW", uint64(xsave.Cwd))
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regs = proc.AppendUint64Register(regs, "SW", uint64(xsave.Swd))
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regs = proc.AppendUint64Register(regs, "TW", uint64(xsave.Ftw))
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regs = proc.AppendUint64Register(regs, "FOP", uint64(xsave.Fop))
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regs = proc.AppendUint64Register(regs, "FIP", xsave.Rip)
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regs = proc.AppendUint64Register(regs, "FDP", xsave.Rdp)
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for i := 0; i < len(xsave.StSpace); i += 4 {
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var buf bytes.Buffer
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binary.Write(&buf, binary.LittleEndian, uint64(xsave.StSpace[i+1])<<32|uint64(xsave.StSpace[i]))
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binary.Write(&buf, binary.LittleEndian, uint16(xsave.StSpace[i+2]))
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("ST(%d)", i/4), buf.Bytes())
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}
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// SSE registers
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regs = proc.AppendUint64Register(regs, "MXCSR", uint64(xsave.Mxcsr))
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regs = proc.AppendUint64Register(regs, "MXCSR_MASK", uint64(xsave.MxcrMask))
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for i := 0; i < len(xsave.XmmSpace); i += 16 {
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n := i / 16
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("XMM%d", n), xsave.XmmSpace[i:i+16])
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if xsave.AvxState {
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("YMM%d", n), xsave.YmmSpace[i:i+16])
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if xsave.Avx512State {
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("ZMM%d", n), xsave.ZmmSpace[n*32:(n+1)*32])
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}
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}
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}
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return regs
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}
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const (
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_XSTATE_MAX_KNOWN_SIZE = 2969
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_XSAVE_HEADER_START = 512
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_XSAVE_HEADER_LEN = 64
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_XSAVE_EXTENDED_REGION_START = 576
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_XSAVE_SSE_REGION_LEN = 416
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_XSAVE_AVX512_ZMM_REGION_START = 1152
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)
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// AMD64XstateRead reads a byte array containing an XSAVE area into regset.
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// If readLegacy is true regset.PtraceFpRegs will be filled with the
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// contents of the legacy region of the XSAVE area.
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// See Section 13.1 (and following) of Intel® 64 and IA-32 Architectures
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// Software Developer’s Manual, Volume 1: Basic Architecture.
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func AMD64XstateRead(xstateargs []byte, readLegacy bool, regset *AMD64Xstate) error {
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if _XSAVE_HEADER_START+_XSAVE_HEADER_LEN >= len(xstateargs) {
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return nil
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}
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if readLegacy {
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rdr := bytes.NewReader(xstateargs[:_XSAVE_HEADER_START])
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if err := binary.Read(rdr, binary.LittleEndian, ®set.AMD64PtraceFpRegs); err != nil {
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return err
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}
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}
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xsaveheader := xstateargs[_XSAVE_HEADER_START : _XSAVE_HEADER_START+_XSAVE_HEADER_LEN]
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xstate_bv := binary.LittleEndian.Uint64(xsaveheader[0:8])
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xcomp_bv := binary.LittleEndian.Uint64(xsaveheader[8:16])
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if xcomp_bv&(1<<63) != 0 {
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// compact format not supported
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return nil
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}
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if xstate_bv&(1<<2) == 0 {
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// AVX state not present
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return nil
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}
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avxstate := xstateargs[_XSAVE_EXTENDED_REGION_START:]
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regset.AvxState = true
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copy(regset.YmmSpace[:], avxstate[:len(regset.YmmSpace)])
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if xstate_bv&(1<<6) == 0 {
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// AVX512 state not present
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return nil
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}
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avx512state := xstateargs[_XSAVE_AVX512_ZMM_REGION_START:]
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regset.Avx512State = true
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copy(regset.ZmmSpace[:], avx512state[:len(regset.ZmmSpace)])
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// TODO(aarzilli): if xstate_bv&(1<<7) is set then xstateargs[1664:2688]
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// contains ZMM16 through ZMM31, those aren't just the higher 256bits, it's
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// the full register so each is 64 bytes (512bits)
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return nil
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}
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