06053a7e4b
When stack watchpoints go out of scope simultaneously they can hide (or duplicate the effect) of other breakpoints (including other watchpoints going out of scope) that are placed on the same physical memory location. This happens because we delete the watchpoint-out-of-scope breakpoint while we are evaluating hit breakpoints, mangling the breaklets list. This commit moves breakpoint deletion out of the watchpoint-out-of-scope condition, delaying it until all hit breakpoints have been evaluated. Also fix bug where on amd64 if all four watchpoints are in use the last one is not checked. Fixes #3739
131 lines
3.1 KiB
Go
131 lines
3.1 KiB
Go
package amd64util
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import (
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"errors"
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"fmt"
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)
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// DebugRegisters represents x86 debug registers described in the Intel 64
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// and IA-32 Architectures Software Developer's Manual, Vol. 3B, section
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// 17.2
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type DebugRegisters struct {
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pAddrs [4]*uint64
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pDR6, pDR7 *uint64
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Dirty bool
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}
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func NewDebugRegisters(pDR0, pDR1, pDR2, pDR3, pDR6, pDR7 *uint64) *DebugRegisters {
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return &DebugRegisters{
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pAddrs: [4]*uint64{pDR0, pDR1, pDR2, pDR3},
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pDR6: pDR6,
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pDR7: pDR7,
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Dirty: false,
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}
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}
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func lenrwBitsOffset(idx uint8) uint8 {
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return 16 + idx*4
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}
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func enableBitOffset(idx uint8) uint8 {
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return idx * 2
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}
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func (drs *DebugRegisters) breakpoint(idx uint8) (addr uint64, read, write bool, sz int) {
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enable := *(drs.pDR7) & (1 << enableBitOffset(idx))
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if enable == 0 {
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return 0, false, false, 0
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}
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addr = *(drs.pAddrs[idx])
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lenrw := (*(drs.pDR7) >> lenrwBitsOffset(idx)) & 0xf
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write = (lenrw & 0x1) != 0
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read = (lenrw & 0x2) != 0
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switch lenrw >> 2 {
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case 0x0:
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sz = 1
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case 0x1:
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sz = 2
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case 0x2:
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sz = 8 // sic
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case 0x3:
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sz = 4
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}
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return addr, read, write, sz
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}
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// SetBreakpoint sets hardware breakpoint at index 'idx' to the specified
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// address, read/write flags and size.
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// If the breakpoint is already in use but the parameters match it does
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// nothing.
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func (drs *DebugRegisters) SetBreakpoint(idx uint8, addr uint64, read, write bool, sz int) error {
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if int(idx) >= len(drs.pAddrs) {
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return fmt.Errorf("hardware breakpoints exhausted")
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}
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curaddr, curread, curwrite, cursz := drs.breakpoint(idx)
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if curaddr != 0 {
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if (curaddr != addr) || (curread != read) || (curwrite != write) || (cursz != sz) {
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return fmt.Errorf("hardware breakpoint %d already in use (address %#x)", idx, curaddr)
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}
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// hardware breakpoint already set
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return nil
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}
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if read && !write {
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return errors.New("break on read only not supported")
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}
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*(drs.pAddrs[idx]) = addr
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var lenrw uint64
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if write {
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lenrw |= 0x1
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}
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if read {
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lenrw |= 0x2
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}
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switch sz {
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case 1:
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// already ok
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case 2:
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lenrw |= 0x1 << 2
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case 4:
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lenrw |= 0x3 << 2
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case 8:
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lenrw |= 0x2 << 2
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default:
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return fmt.Errorf("data breakpoint of size %d not supported", sz)
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}
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*(drs.pDR7) &^= (0xf << lenrwBitsOffset(idx)) // clear old settings
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*(drs.pDR7) |= lenrw << lenrwBitsOffset(idx)
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*(drs.pDR7) |= 1 << enableBitOffset(idx) // enable
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drs.Dirty = true
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return nil
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}
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// ClearBreakpoint disables the hardware breakpoint at index 'idx'. If the
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// breakpoint was already disabled it does nothing.
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func (drs *DebugRegisters) ClearBreakpoint(idx uint8) {
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if *(drs.pDR7)&(1<<enableBitOffset(idx)) == 0 {
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return
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}
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*(drs.pDR7) &^= (1 << enableBitOffset(idx))
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drs.Dirty = true
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}
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// GetActiveBreakpoint returns the active hardware breakpoint and resets the
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// condition flags.
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func (drs *DebugRegisters) GetActiveBreakpoint() (ok bool, idx uint8) {
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for idx := uint8(0); idx <= 3; idx++ {
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enable := *(drs.pDR7) & (1 << enableBitOffset(idx))
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if enable == 0 {
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continue
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}
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if *(drs.pDR6)&(1<<idx) != 0 {
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*drs.pDR6 &^= 0xf // it is our responsibility to clear the condition bits
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drs.Dirty = true
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return true, idx
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}
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}
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return false, 0
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}
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