7e2660e7de
The ARM64 left the vendor directory in an inconsistent state, go1.13 doesn't care so we didn't catch it but go1.14 does.
703 lines
16 KiB
Go
703 lines
16 KiB
Go
// Copyright 2017 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package arm64asm
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import (
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"fmt"
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"io"
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"sort"
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"strings"
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)
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// GoSyntax returns the Go assembler syntax for the instruction.
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// The syntax was originally defined by Plan 9.
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// The pc is the program counter of the instruction, used for
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// expanding PC-relative addresses into absolute ones.
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// The symname function queries the symbol table for the program
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// being disassembled. Given a target address it returns the name
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// and base address of the symbol containing the target, if any;
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// otherwise it returns "", 0.
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// The reader text should read from the text segment using text addresses
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// as offsets; it is used to display pc-relative loads as constant loads.
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func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string {
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if symname == nil {
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symname = func(uint64) (string, uint64) { return "", 0 }
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}
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var args []string
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for _, a := range inst.Args {
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if a == nil {
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break
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}
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args = append(args, plan9Arg(&inst, pc, symname, a))
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}
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op := inst.Op.String()
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switch inst.Op {
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case LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW:
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// Check for PC-relative load.
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if offset, ok := inst.Args[1].(PCRel); ok {
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addr := pc + uint64(offset)
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if _, ok := inst.Args[0].(Reg); !ok {
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break
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}
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if s, base := symname(addr); s != "" && addr == base {
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args[1] = fmt.Sprintf("$%s(SB)", s)
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}
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}
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}
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// Move addressing mode into opcode suffix.
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suffix := ""
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switch inst.Op {
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case LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH, STUR, STURB, STURH, LD1, ST1:
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switch mem := inst.Args[1].(type) {
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case MemImmediate:
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switch mem.Mode {
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case AddrOffset:
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// no suffix
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case AddrPreIndex:
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suffix = ".W"
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case AddrPostIndex, AddrPostReg:
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suffix = ".P"
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}
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}
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case STP, LDP:
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switch mem := inst.Args[2].(type) {
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case MemImmediate:
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switch mem.Mode {
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case AddrOffset:
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// no suffix
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case AddrPreIndex:
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suffix = ".W"
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case AddrPostIndex:
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suffix = ".P"
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}
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}
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}
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switch inst.Op {
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case BL:
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return "CALL " + args[0]
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case BLR:
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r := inst.Args[0].(Reg)
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regno := uint16(r) & 31
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return fmt.Sprintf("CALL (R%d)", regno)
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case RET:
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if r, ok := inst.Args[0].(Reg); ok && r == X30 {
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return "RET"
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}
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case B:
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if cond, ok := inst.Args[0].(Cond); ok {
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return "B" + cond.String() + " " + args[1]
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}
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return "JMP" + " " + args[0]
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case BR:
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r := inst.Args[0].(Reg)
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regno := uint16(r) & 31
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return fmt.Sprintf("JMP (R%d)", regno)
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case MOV:
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rno := -1
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switch a := inst.Args[0].(type) {
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case Reg:
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rno = int(a)
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case RegSP:
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rno = int(a)
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case RegisterWithArrangementAndIndex:
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op = "VMOV"
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case RegisterWithArrangement:
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op = "VMOV"
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}
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if rno >= 0 && rno <= int(WZR) {
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op = "MOVW"
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} else if rno >= int(X0) && rno <= int(XZR) {
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op = "MOVD"
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}
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if _, ok := inst.Args[1].(RegisterWithArrangementAndIndex); ok {
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op = "VMOV"
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}
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case LDR:
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var rno uint16
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if r, ok := inst.Args[0].(Reg); ok {
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rno = uint16(r)
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} else {
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rno = uint16(inst.Args[0].(RegSP))
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}
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if rno <= uint16(WZR) {
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op = "MOVWU" + suffix
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} else if rno >= uint16(S0) && rno <= uint16(S31) {
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op = "FMOVS" + suffix
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args[0] = fmt.Sprintf("F%d", rno&31)
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = "FMOVD" + suffix
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args[0] = fmt.Sprintf("F%d", rno&31)
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} else {
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op = "MOVD" + suffix
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}
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case LDRB:
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op = "MOVBU" + suffix
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case LDRH:
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op = "MOVHU" + suffix
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case LDRSW:
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op = "MOVW" + suffix
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case LDRSB:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op = "MOVBW" + suffix
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} else {
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op = "MOVB" + suffix
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}
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}
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case LDRSH:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op = "MOVHW" + suffix
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} else {
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op = "MOVH" + suffix
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}
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}
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case STR, STUR:
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var rno uint16
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if r, ok := inst.Args[0].(Reg); ok {
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rno = uint16(r)
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} else {
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rno = uint16(inst.Args[0].(RegSP))
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}
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if rno <= uint16(WZR) {
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op = "MOVW" + suffix
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} else if rno >= uint16(S0) && rno <= uint16(S31) {
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op = "FMOVS" + suffix
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args[0] = fmt.Sprintf("F%d", rno&31)
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = "FMOVD" + suffix
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args[0] = fmt.Sprintf("F%d", rno&31)
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} else {
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op = "MOVD" + suffix
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}
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args[0], args[1] = args[1], args[0]
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case STRB, STURB:
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op = "MOVB" + suffix
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args[0], args[1] = args[1], args[0]
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case STRH, STURH:
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op = "MOVH" + suffix
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args[0], args[1] = args[1], args[0]
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case TBNZ, TBZ:
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args[0], args[1], args[2] = args[2], args[0], args[1]
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case MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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args[2], args[3] = args[3], args[2]
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case STLR:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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args[0], args[1] = args[1], args[0]
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case STLRB, STLRH:
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args[0], args[1] = args[1], args[0]
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case STLXR, STXR:
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if r, ok := inst.Args[1].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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args[1], args[2] = args[2], args[1]
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case STLXRB, STLXRH, STXRB, STXRH:
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args[1], args[2] = args[2], args[1]
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case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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args[1], args[2], args[3] = args[3], args[1], args[2]
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case LDAXP, LDXP:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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fallthrough
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case STP, LDP:
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args[0] = fmt.Sprintf("(%s, %s)", args[0], args[1])
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args[1] = args[2]
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if op == "STP" {
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op = op + suffix
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return op + " " + args[0] + ", " + args[1]
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} else if op == "LDP" {
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op = op + suffix
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return op + " " + args[1] + ", " + args[0]
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} else if op == "LDAXP" || op == "LDXP" || op == "LDAXPW" || op == "LDXPW" {
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return op + " " + args[1] + ", " + args[0]
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}
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case STLXP, STXP:
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if r, ok := inst.Args[1].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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args[1] = fmt.Sprintf("(%s, %s)", args[1], args[2])
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args[2] = args[3]
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return op + " " + args[1] + ", " + args[2] + ", " + args[0]
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case FCCMP, FCCMPE:
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args[0], args[1] = args[1], args[0]
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fallthrough
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case FCMP, FCMPE:
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if _, ok := inst.Args[1].(Imm); ok {
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args[1] = "$(0.0)"
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}
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fallthrough
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case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL, FMADD, FMSUB, FNMADD, FNMSUB:
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if strings.HasSuffix(op, "MADD") || strings.HasSuffix(op, "MSUB") {
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args[2], args[3] = args[3], args[2]
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}
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno >= uint16(S0) && rno <= uint16(S31) {
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op = fmt.Sprintf("%sS", op)
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = fmt.Sprintf("%sD", op)
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}
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}
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case FCVT:
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for i := 1; i >= 0; i-- {
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if r, ok := inst.Args[i].(Reg); ok {
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rno := uint16(r)
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if rno >= uint16(H0) && rno <= uint16(H31) {
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op = fmt.Sprintf("%sH", op)
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} else if rno >= uint16(S0) && rno <= uint16(S31) {
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op = fmt.Sprintf("%sS", op)
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = fmt.Sprintf("%sD", op)
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}
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}
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}
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case FABS, FNEG, FSQRT, FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX, FRINTI:
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if r, ok := inst.Args[1].(Reg); ok {
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rno := uint16(r)
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if rno >= uint16(S0) && rno <= uint16(S31) {
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op = fmt.Sprintf("%sS", op)
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = fmt.Sprintf("%sD", op)
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}
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}
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case FCVTZS, FCVTZU, SCVTF, UCVTF:
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if _, ok := inst.Args[2].(Imm); !ok {
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for i := 1; i >= 0; i-- {
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if r, ok := inst.Args[i].(Reg); ok {
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rno := uint16(r)
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if rno >= uint16(S0) && rno <= uint16(S31) {
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op = fmt.Sprintf("%sS", op)
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = fmt.Sprintf("%sD", op)
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} else if rno <= uint16(WZR) {
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op += "W"
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}
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}
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}
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}
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case FMOV:
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for i := 0; i <= 1; i++ {
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if r, ok := inst.Args[i].(Reg); ok {
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rno := uint16(r)
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if rno >= uint16(S0) && rno <= uint16(S31) {
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op = fmt.Sprintf("%sS", op)
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break
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} else if rno >= uint16(D0) && rno <= uint16(D31) {
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op = fmt.Sprintf("%sD", op)
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break
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}
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}
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}
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case SYSL:
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op1 := int(inst.Args[1].(Imm).Imm)
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cn := int(inst.Args[2].(Imm_c))
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cm := int(inst.Args[3].(Imm_c))
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op2 := int(inst.Args[4].(Imm).Imm)
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sysregno := int32(op1<<16 | cn<<12 | cm<<8 | op2<<5)
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args[1] = fmt.Sprintf("$%d", sysregno)
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return op + " " + args[1] + ", " + args[0]
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case CBNZ, CBZ:
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if r, ok := inst.Args[0].(Reg); ok {
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rno := uint16(r)
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if rno <= uint16(WZR) {
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op += "W"
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}
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}
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args[0], args[1] = args[1], args[0]
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case ADR, ADRP:
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addr := int64(inst.Args[1].(PCRel))
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args[1] = fmt.Sprintf("%d(PC)", addr)
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case MSR:
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args[0] = inst.Args[0].String()
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case ST1:
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op = fmt.Sprintf("V%s", op) + suffix
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args[0], args[1] = args[1], args[0]
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case LD1:
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op = fmt.Sprintf("V%s", op) + suffix
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case UMOV:
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op = "VMOV"
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default:
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index := sort.SearchStrings(noSuffixOpSet, op)
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if !(index < len(noSuffixOpSet) && noSuffixOpSet[index] == op) {
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rno := -1
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switch a := inst.Args[0].(type) {
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case Reg:
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rno = int(a)
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case RegSP:
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rno = int(a)
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case RegisterWithArrangement:
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op = fmt.Sprintf("V%s", op)
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}
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if rno >= int(B0) && rno <= int(Q31) && !strings.HasPrefix(op, "F") {
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op = fmt.Sprintf("V%s", op)
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}
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if rno >= 0 && rno <= int(WZR) {
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// Add "w" to opcode suffix.
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op += "W"
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}
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}
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op = op + suffix
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}
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// conditional instructions, replace args.
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if _, ok := inst.Args[3].(Cond); ok {
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if _, ok := inst.Args[2].(Reg); ok {
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args[1], args[2] = args[2], args[1]
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} else {
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args[0], args[2] = args[2], args[0]
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}
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}
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// Reverse args, placing dest last.
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for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 {
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args[i], args[j] = args[j], args[i]
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}
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if args != nil {
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op += " " + strings.Join(args, ", ")
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}
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return op
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}
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// No need add "W" to opcode suffix.
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// Opcode must be inserted in ascending order.
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var noSuffixOpSet = strings.Fields(`
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AESD
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AESE
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AESIMC
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AESMC
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CRC32B
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CRC32CB
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CRC32CH
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CRC32CW
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CRC32CX
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CRC32H
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CRC32W
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CRC32X
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LDARB
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LDARH
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LDAXRB
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LDAXRH
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LDTRH
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LDXRB
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LDXRH
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SHA1C
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SHA1H
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SHA1M
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SHA1P
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SHA1SU0
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SHA1SU1
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SHA256H
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SHA256H2
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SHA256SU0
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SHA256SU1
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`)
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func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
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switch a := arg.(type) {
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case Imm:
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return fmt.Sprintf("$%d", uint32(a.Imm))
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case Imm64:
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return fmt.Sprintf("$%d", int64(a.Imm))
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case ImmShift:
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if a.shift == 0 {
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return fmt.Sprintf("$%d", a.imm)
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}
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return fmt.Sprintf("$(%d<<%d)", a.imm, a.shift)
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case PCRel:
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addr := int64(pc) + int64(a)
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if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base {
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return fmt.Sprintf("%s(SB)", s)
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}
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return fmt.Sprintf("%d(PC)", a/4)
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case Reg:
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regenum := uint16(a)
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regno := uint16(a) & 31
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if regenum >= uint16(B0) && regenum <= uint16(D31) {
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if strings.HasPrefix(inst.Op.String(), "F") || strings.HasSuffix(inst.Op.String(), "CVTF") {
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// FP registers are the same ones as SIMD registers
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// Print Fn for scalar variant to align with assembler (e.g., FCVT, SCVTF, UCVTF, etc.)
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return fmt.Sprintf("F%d", regno)
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} else {
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return fmt.Sprintf("V%d", regno)
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}
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} else if regenum >= uint16(Q0) && regenum <= uint16(Q31) {
|
|
// Print Vn to align with assembler (e.g., SHA256H)
|
|
return fmt.Sprintf("V%d", regno)
|
|
}
|
|
|
|
if regno == 31 {
|
|
return "ZR"
|
|
}
|
|
return fmt.Sprintf("R%d", regno)
|
|
|
|
case RegSP:
|
|
regno := uint16(a) & 31
|
|
if regno == 31 {
|
|
return "RSP"
|
|
}
|
|
return fmt.Sprintf("R%d", regno)
|
|
|
|
case RegExtshiftAmount:
|
|
reg := ""
|
|
regno := uint16(a.reg) & 31
|
|
if regno == 31 {
|
|
reg = "ZR"
|
|
} else {
|
|
reg = fmt.Sprintf("R%d", uint16(a.reg)&31)
|
|
}
|
|
extshift := ""
|
|
amount := ""
|
|
if a.extShift != ExtShift(0) {
|
|
switch a.extShift {
|
|
default:
|
|
extshift = "." + a.extShift.String()
|
|
|
|
case lsl:
|
|
extshift = "<<"
|
|
amount = fmt.Sprintf("%d", a.amount)
|
|
return reg + extshift + amount
|
|
|
|
case lsr:
|
|
extshift = ">>"
|
|
amount = fmt.Sprintf("%d", a.amount)
|
|
return reg + extshift + amount
|
|
|
|
case asr:
|
|
extshift = "->"
|
|
amount = fmt.Sprintf("%d", a.amount)
|
|
return reg + extshift + amount
|
|
case ror:
|
|
extshift = "@>"
|
|
amount = fmt.Sprintf("%d", a.amount)
|
|
return reg + extshift + amount
|
|
}
|
|
if a.amount != 0 {
|
|
amount = fmt.Sprintf("<<%d", a.amount)
|
|
}
|
|
}
|
|
return reg + extshift + amount
|
|
|
|
case MemImmediate:
|
|
off := ""
|
|
base := ""
|
|
regno := uint16(a.Base) & 31
|
|
if regno == 31 {
|
|
base = "(RSP)"
|
|
} else {
|
|
base = fmt.Sprintf("(R%d)", regno)
|
|
}
|
|
if a.imm != 0 && a.Mode != AddrPostReg {
|
|
off = fmt.Sprintf("%d", a.imm)
|
|
} else if a.Mode == AddrPostReg {
|
|
postR := fmt.Sprintf("(R%d)", a.imm)
|
|
return base + postR
|
|
}
|
|
return off + base
|
|
|
|
case MemExtend:
|
|
base := ""
|
|
index := ""
|
|
indexreg := ""
|
|
regno := uint16(a.Base) & 31
|
|
if regno == 31 {
|
|
base = "(RSP)"
|
|
} else {
|
|
base = fmt.Sprintf("(R%d)", regno)
|
|
}
|
|
regno = uint16(a.Index) & 31
|
|
if regno == 31 {
|
|
indexreg = "ZR"
|
|
} else {
|
|
indexreg = fmt.Sprintf("R%d", regno)
|
|
}
|
|
|
|
if a.Extend == lsl {
|
|
// a.Amount indicates the index shift amount, encoded in "S" field.
|
|
// a.ShiftMustBeZero is set true when the index shift amount must be 0,
|
|
// even if the a.Amount field is not 0.
|
|
// When a.ShiftMustBeZero is ture, GNU syntax prints #0 shift amount if
|
|
// "S" equals to 1, or does not print #0 shift amount if "S" equals to 0.
|
|
// Go syntax should never print a zero index shift amount.
|
|
if a.Amount != 0 && !a.ShiftMustBeZero {
|
|
index = fmt.Sprintf("(%s<<%d)", indexreg, a.Amount)
|
|
} else {
|
|
index = fmt.Sprintf("(%s)", indexreg)
|
|
}
|
|
} else {
|
|
if a.Amount != 0 && !a.ShiftMustBeZero {
|
|
index = fmt.Sprintf("(%s.%s<<%d)", indexreg, a.Extend.String(), a.Amount)
|
|
} else {
|
|
index = fmt.Sprintf("(%s.%s)", indexreg, a.Extend.String())
|
|
}
|
|
}
|
|
|
|
return base + index
|
|
|
|
case Cond:
|
|
switch arg.String() {
|
|
case "CS":
|
|
return "HS"
|
|
case "CC":
|
|
return "LO"
|
|
}
|
|
|
|
case Imm_clrex:
|
|
return fmt.Sprintf("$%d", uint32(a))
|
|
|
|
case Imm_dcps:
|
|
return fmt.Sprintf("$%d", uint32(a))
|
|
|
|
case Imm_option:
|
|
return fmt.Sprintf("$%d", uint8(a))
|
|
|
|
case Imm_hint:
|
|
return fmt.Sprintf("$%d", uint8(a))
|
|
|
|
case Imm_fp:
|
|
var s, pre, numerator, denominator int16
|
|
var result float64
|
|
if a.s == 0 {
|
|
s = 1
|
|
} else {
|
|
s = -1
|
|
}
|
|
pre = s * int16(16+a.pre)
|
|
if a.exp > 0 {
|
|
numerator = (pre << uint8(a.exp))
|
|
denominator = 16
|
|
} else {
|
|
numerator = pre
|
|
denominator = (16 << uint8(-1*a.exp))
|
|
}
|
|
result = float64(numerator) / float64(denominator)
|
|
return strings.TrimRight(fmt.Sprintf("$%f", result), "0")
|
|
|
|
case RegisterWithArrangement:
|
|
result := a.r.String()
|
|
arrange := a.a.String()
|
|
c := []rune(arrange)
|
|
switch len(c) {
|
|
case 3:
|
|
c[1], c[2] = c[2], c[1] // .8B -> .B8
|
|
case 4:
|
|
c[1], c[2], c[3] = c[3], c[1], c[2] // 16B -> B16
|
|
}
|
|
arrange = string(c)
|
|
result += arrange
|
|
if a.cnt > 0 {
|
|
result = "[" + result
|
|
for i := 1; i < int(a.cnt); i++ {
|
|
cur := V0 + Reg((uint16(a.r)-uint16(V0)+uint16(i))&31)
|
|
result += ", " + cur.String() + arrange
|
|
}
|
|
result += "]"
|
|
}
|
|
return result
|
|
|
|
case RegisterWithArrangementAndIndex:
|
|
result := a.r.String()
|
|
arrange := a.a.String()
|
|
result += arrange
|
|
if a.cnt > 1 {
|
|
result = "[" + result
|
|
for i := 1; i < int(a.cnt); i++ {
|
|
cur := V0 + Reg((uint16(a.r)-uint16(V0)+uint16(i))&31)
|
|
result += ", " + cur.String() + arrange
|
|
}
|
|
result += "]"
|
|
}
|
|
return fmt.Sprintf("%s[%d]", result, a.index)
|
|
|
|
case Systemreg:
|
|
return fmt.Sprintf("$%d", uint32(a.op0&1)<<14|uint32(a.op1&7)<<11|uint32(a.cn&15)<<7|uint32(a.cm&15)<<3|uint32(a.op2)&7)
|
|
|
|
case Imm_prfop:
|
|
if strings.Contains(a.String(), "#") {
|
|
return fmt.Sprintf("$%d", a)
|
|
}
|
|
}
|
|
|
|
return strings.ToUpper(arg.String())
|
|
}
|