ebc3e61367
* enable func call injection on delve for ppc64le * Function call injection on Delve/ppc64le, modified DWARF encoding and decoding for floating point registers to make floatsum test work * Function call injection on Delve/ppc64le cleanup * skip PIE tests for function call injection on other packages * Address review comments * accounted for additional skipped PIE tests for function call injection * Code cleanup and undoing revert of previous commit * Enable function call injection only on 1.22 and above and some cleanup * additional cleanup, go fmt run * Debug function call tests fail on ppc64le/PIE mode adjusted the backup_test_health.md file accordingly
117 lines
3.2 KiB
Go
117 lines
3.2 KiB
Go
package regnum
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import "fmt"
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// The mapping between hardware registers and DWARF registers is specified
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// in the 64-Bit ELF V2 ABI Specification of the Power Architecture in section
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// 2.4 DWARF Definition
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// https://openpowerfoundation.org/specifications/64bitelfabi/
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const (
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// General Purpose Registers: from R0 to R31
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PPC64LE_FIRST_GPR = 0
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PPC64LE_R0 = PPC64LE_FIRST_GPR
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PPC64LE_LAST_GPR = 31
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// Floating point registers: from F0 to F31
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PPC64LE_FIRST_FPR = 32
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PPC64LE_F0 = PPC64LE_FIRST_FPR
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PPC64LE_LAST_FPR = 63
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// Vector (Altivec/VMX) registers: from V0 to V31
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PPC64LE_FIRST_VMX = 77
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PPC64LE_V0 = PPC64LE_FIRST_VMX
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PPC64LE_LAST_VMX = 108
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// Vector Scalar (VSX) registers: from VS32 to VS63
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// On ppc64le these are mapped to F0 to F31
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PPC64LE_FIRST_VSX = 32
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PPC64LE_VS0 = PPC64LE_FIRST_VSX
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PPC64LE_LAST_VSX = 63
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// Condition Registers: from CR0 to CR7
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PPC64LE_CR0 = 0
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// Special registers
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PPC64LE_SP = 1 // Stack frame pointer: Gpr[1]
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PPC64LE_PC = 12 // The documentation refers to this as the CIA (Current Instruction Address)
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PPC64LE_LR = 65 // Link register
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)
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func PPC64LEToName(num uint64) string {
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switch {
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case num == PPC64LE_SP:
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return "SP"
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case num == PPC64LE_PC:
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return "PC"
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case num == PPC64LE_LR:
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return "LR"
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case isGPR(num):
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return fmt.Sprintf("r%d", int(num-PPC64LE_FIRST_GPR))
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case isFPR(num):
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return fmt.Sprintf("f%d", int(num-PPC64LE_FIRST_FPR))
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case isVMX(num):
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return fmt.Sprintf("v%d", int(num-PPC64LE_FIRST_VMX))
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case isVSX(num):
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return fmt.Sprintf("vs%d", int(num-PPC64LE_FIRST_VSX))
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default:
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return fmt.Sprintf("unknown%d", num)
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}
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}
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// PPC64LEMaxRegNum is 172 registers in total, across 4 categories:
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// General Purpose Registers or GPR (32 GPR + 9 special registers)
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// Floating Point Registers or FPR (32 FPR + 1 special register)
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// Altivec/VMX Registers or VMX (32 VMX + 2 special registers)
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// VSX Registers or VSX (64 VSX)
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// Documentation: https://lldb.llvm.org/cpp_reference/RegisterContextPOSIX__ppc64le_8cpp_source.html
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func PPC64LEMaxRegNum() uint64 {
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return 172
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}
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func isGPR(num uint64) bool {
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return num < PPC64LE_LAST_GPR
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}
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func isFPR(num uint64) bool {
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return num >= PPC64LE_FIRST_FPR && num <= PPC64LE_LAST_FPR
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}
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func isVMX(num uint64) bool {
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return num >= PPC64LE_FIRST_VMX && num <= PPC64LE_LAST_VMX
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}
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func isVSX(num uint64) bool {
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return num >= PPC64LE_FIRST_VSX && num <= PPC64LE_LAST_VSX
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}
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var PPC64LENameToDwarf = func() map[string]int {
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r := make(map[string]int)
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r["nip"] = PPC64LE_PC
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r["sp"] = PPC64LE_SP
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r["bp"] = PPC64LE_SP
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r["link"] = PPC64LE_LR
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// General Purpose Registers: from R0 to R31
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for i := 0; i <= 31; i++ {
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r[fmt.Sprintf("r%d", i)] = PPC64LE_R0 + i
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}
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// Floating point registers: from F0 to F31
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for i := 0; i <= 31; i++ {
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r[fmt.Sprintf("f%d", i)] = PPC64LE_F0 + i
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}
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// Vector (Altivec/VMX) registers: from V0 to V31
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for i := 0; i <= 31; i++ {
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r[fmt.Sprintf("v%d", i)] = PPC64LE_V0 + i
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}
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// Vector Scalar (VSX) registers: from VS0 to VS63
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for i := 0; i <= 63; i++ {
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r[fmt.Sprintf("vs%d", i)] = PPC64LE_VS0 + i
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}
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// Condition Registers: from CR0 to CR7
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for i := 0; i <= 7; i++ {
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r[fmt.Sprintf("cr%d", i)] = PPC64LE_CR0 + i
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}
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return r
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}()
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