910f90c3c8
On macOS 10.14 Apple changed the command line tools so that system headers now need to be manually installed. Instead of adding one extra install step to the install procedure add a build tag to allow compilation of delve without the native backend on macOS. By default (i.e. when using `go get`) this is how delve will be compiled on macOS, the make script is changed to enable compiling the native backend if the required dependencies have been installed. Insure that both configuration still build correctly on Travis CI and change the documentation to describe how to compile the native backend and that it isn't normally needed. Fixes #1359
376 lines
9.8 KiB
Go
376 lines
9.8 KiB
Go
//+build darwin,macnative
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package native
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// #include "threads_darwin.h"
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import "C"
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import (
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"encoding/binary"
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"errors"
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"fmt"
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"unsafe"
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"golang.org/x/arch/x86/x86asm"
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"github.com/derekparker/delve/pkg/proc"
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)
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// Regs represents CPU registers on an AMD64 processor.
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type Regs struct {
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rax uint64
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rbx uint64
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rcx uint64
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rdx uint64
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rdi uint64
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rsi uint64
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rbp uint64
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rsp uint64
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r8 uint64
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r9 uint64
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r10 uint64
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r11 uint64
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r12 uint64
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r13 uint64
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r14 uint64
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r15 uint64
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rip uint64
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rflags uint64
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cs uint64
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fs uint64
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gs uint64
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gsBase uint64
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fpregs []proc.Register
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}
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func (r *Regs) Slice() []proc.Register {
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var regs = []struct {
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k string
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v uint64
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}{
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{"Rip", r.rip},
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{"Rsp", r.rsp},
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{"Rax", r.rax},
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{"Rbx", r.rbx},
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{"Rcx", r.rcx},
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{"Rdx", r.rdx},
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{"Rdi", r.rdi},
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{"Rsi", r.rsi},
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{"Rbp", r.rbp},
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{"R8", r.r8},
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{"R9", r.r9},
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{"R10", r.r10},
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{"R11", r.r11},
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{"R12", r.r12},
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{"R13", r.r13},
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{"R14", r.r14},
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{"R15", r.r15},
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{"Rflags", r.rflags},
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{"Cs", r.cs},
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{"Fs", r.fs},
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{"Gs", r.gs},
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{"Gs_base", r.gsBase},
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}
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out := make([]proc.Register, 0, len(regs)+len(r.fpregs))
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for _, reg := range regs {
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if reg.k == "Rflags" {
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out = proc.AppendEflagReg(out, reg.k, reg.v)
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} else {
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out = proc.AppendQwordReg(out, reg.k, reg.v)
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}
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}
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out = append(out, r.fpregs...)
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return out
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}
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// PC returns the current program counter
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// i.e. the RIP CPU register.
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func (r *Regs) PC() uint64 {
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return r.rip
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}
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// SP returns the stack pointer location,
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// i.e. the RSP register.
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func (r *Regs) SP() uint64 {
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return r.rsp
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}
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func (r *Regs) BP() uint64 {
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return r.rbp
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}
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// CX returns the value of the RCX register.
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func (r *Regs) CX() uint64 {
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return r.rcx
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}
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// TLS returns the value of the register
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// that contains the location of the thread
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// local storage segment.
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func (r *Regs) TLS() uint64 {
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return r.gsBase
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}
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func (r *Regs) GAddr() (uint64, bool) {
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return 0, false
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}
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// SetPC sets the RIP register to the value specified by `pc`.
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func (thread *Thread) SetPC(pc uint64) error {
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kret := C.set_pc(thread.os.threadAct, C.uint64_t(pc))
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if kret != C.KERN_SUCCESS {
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return fmt.Errorf("could not set pc")
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}
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return nil
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}
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// SetSP sets the RSP register to the value specified by `pc`.
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func (thread *Thread) SetSP(sp uint64) error {
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return errors.New("not implemented")
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}
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func (thread *Thread) SetDX(dx uint64) error {
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return errors.New("not implemented")
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}
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func (r *Regs) Get(n int) (uint64, error) {
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reg := x86asm.Reg(n)
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const (
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mask8 = 0x000f
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mask16 = 0x00ff
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mask32 = 0xffff
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)
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switch reg {
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// 8-bit
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case x86asm.AL:
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return r.rax & mask8, nil
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case x86asm.CL:
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return r.rcx & mask8, nil
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case x86asm.DL:
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return r.rdx & mask8, nil
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case x86asm.BL:
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return r.rbx & mask8, nil
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case x86asm.AH:
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return (r.rax >> 8) & mask8, nil
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case x86asm.CH:
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return (r.rcx >> 8) & mask8, nil
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case x86asm.DH:
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return (r.rdx >> 8) & mask8, nil
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case x86asm.BH:
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return (r.rbx >> 8) & mask8, nil
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case x86asm.SPB:
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return r.rsp & mask8, nil
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case x86asm.BPB:
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return r.rbp & mask8, nil
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case x86asm.SIB:
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return r.rsi & mask8, nil
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case x86asm.DIB:
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return r.rdi & mask8, nil
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case x86asm.R8B:
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return r.r8 & mask8, nil
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case x86asm.R9B:
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return r.r9 & mask8, nil
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case x86asm.R10B:
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return r.r10 & mask8, nil
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case x86asm.R11B:
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return r.r11 & mask8, nil
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case x86asm.R12B:
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return r.r12 & mask8, nil
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case x86asm.R13B:
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return r.r13 & mask8, nil
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case x86asm.R14B:
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return r.r14 & mask8, nil
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case x86asm.R15B:
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return r.r15 & mask8, nil
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// 16-bit
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case x86asm.AX:
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return r.rax & mask16, nil
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case x86asm.CX:
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return r.rcx & mask16, nil
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case x86asm.DX:
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return r.rdx & mask16, nil
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case x86asm.BX:
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return r.rbx & mask16, nil
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case x86asm.SP:
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return r.rsp & mask16, nil
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case x86asm.BP:
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return r.rbp & mask16, nil
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case x86asm.SI:
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return r.rsi & mask16, nil
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case x86asm.DI:
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return r.rdi & mask16, nil
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case x86asm.R8W:
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return r.r8 & mask16, nil
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case x86asm.R9W:
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return r.r9 & mask16, nil
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case x86asm.R10W:
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return r.r10 & mask16, nil
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case x86asm.R11W:
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return r.r11 & mask16, nil
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case x86asm.R12W:
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return r.r12 & mask16, nil
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case x86asm.R13W:
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return r.r13 & mask16, nil
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case x86asm.R14W:
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return r.r14 & mask16, nil
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case x86asm.R15W:
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return r.r15 & mask16, nil
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// 32-bit
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case x86asm.EAX:
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return r.rax & mask32, nil
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case x86asm.ECX:
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return r.rcx & mask32, nil
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case x86asm.EDX:
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return r.rdx & mask32, nil
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case x86asm.EBX:
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return r.rbx & mask32, nil
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case x86asm.ESP:
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return r.rsp & mask32, nil
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case x86asm.EBP:
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return r.rbp & mask32, nil
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case x86asm.ESI:
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return r.rsi & mask32, nil
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case x86asm.EDI:
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return r.rdi & mask32, nil
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case x86asm.R8L:
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return r.r8 & mask32, nil
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case x86asm.R9L:
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return r.r9 & mask32, nil
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case x86asm.R10L:
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return r.r10 & mask32, nil
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case x86asm.R11L:
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return r.r11 & mask32, nil
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case x86asm.R12L:
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return r.r12 & mask32, nil
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case x86asm.R13L:
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return r.r13 & mask32, nil
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case x86asm.R14L:
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return r.r14 & mask32, nil
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case x86asm.R15L:
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return r.r15 & mask32, nil
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// 64-bit
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case x86asm.RAX:
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return r.rax, nil
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case x86asm.RCX:
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return r.rcx, nil
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case x86asm.RDX:
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return r.rdx, nil
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case x86asm.RBX:
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return r.rbx, nil
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case x86asm.RSP:
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return r.rsp, nil
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case x86asm.RBP:
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return r.rbp, nil
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case x86asm.RSI:
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return r.rsi, nil
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case x86asm.RDI:
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return r.rdi, nil
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case x86asm.R8:
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return r.r8, nil
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case x86asm.R9:
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return r.r9, nil
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case x86asm.R10:
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return r.r10, nil
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case x86asm.R11:
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return r.r11, nil
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case x86asm.R12:
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return r.r12, nil
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case x86asm.R13:
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return r.r13, nil
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case x86asm.R14:
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return r.r14, nil
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case x86asm.R15:
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return r.r15, nil
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}
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return 0, proc.ErrUnknownRegister
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}
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func registers(thread *Thread, floatingPoint bool) (proc.Registers, error) {
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var state C.x86_thread_state64_t
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var identity C.thread_identifier_info_data_t
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kret := C.get_registers(C.mach_port_name_t(thread.os.threadAct), &state)
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if kret != C.KERN_SUCCESS {
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return nil, fmt.Errorf("could not get registers")
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}
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kret = C.get_identity(C.mach_port_name_t(thread.os.threadAct), &identity)
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if kret != C.KERN_SUCCESS {
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return nil, fmt.Errorf("could not get thread identity informations")
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}
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/*
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thread_identifier_info::thread_handle contains the base of the
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thread-specific data area, which on x86 and x86_64 is the thread’s base
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address of the %gs segment. 10.9.2 xnu-2422.90.20/osfmk/kern/thread.c
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thread_info_internal() gets the value from
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machine_thread::cthread_self, which is the same value used to set the
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%gs base in xnu-2422.90.20/osfmk/i386/pcb_native.c
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act_machine_switch_pcb().
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--
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comment copied from chromium's crashpad
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https://chromium.googlesource.com/crashpad/crashpad/+/master/snapshot/mac/process_reader.cc
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*/
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regs := &Regs{
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rax: uint64(state.__rax),
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rbx: uint64(state.__rbx),
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rcx: uint64(state.__rcx),
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rdx: uint64(state.__rdx),
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rdi: uint64(state.__rdi),
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rsi: uint64(state.__rsi),
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rbp: uint64(state.__rbp),
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rsp: uint64(state.__rsp),
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r8: uint64(state.__r8),
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r9: uint64(state.__r9),
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r10: uint64(state.__r10),
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r11: uint64(state.__r11),
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r12: uint64(state.__r12),
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r13: uint64(state.__r13),
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r14: uint64(state.__r14),
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r15: uint64(state.__r15),
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rip: uint64(state.__rip),
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rflags: uint64(state.__rflags),
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cs: uint64(state.__cs),
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fs: uint64(state.__fs),
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gs: uint64(state.__gs),
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gsBase: uint64(identity.thread_handle),
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}
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if floatingPoint {
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// https://opensource.apple.com/source/xnu/xnu-792.13.8/osfmk/mach/i386/thread_status.h?txt
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var fpstate C.x86_float_state64_t
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kret = C.get_fpu_registers(C.mach_port_name_t(thread.os.threadAct), &fpstate)
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if kret != C.KERN_SUCCESS {
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return nil, fmt.Errorf("could not get floating point registers")
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}
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regs.fpregs = proc.AppendWordReg(regs.fpregs, "CW", *((*uint16)(unsafe.Pointer(&fpstate.__fpu_fcw))))
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regs.fpregs = proc.AppendWordReg(regs.fpregs, "SW", *((*uint16)(unsafe.Pointer(&fpstate.__fpu_fsw))))
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regs.fpregs = proc.AppendWordReg(regs.fpregs, "TW", uint16(fpstate.__fpu_ftw))
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regs.fpregs = proc.AppendWordReg(regs.fpregs, "FOP", uint16(fpstate.__fpu_fop))
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regs.fpregs = proc.AppendQwordReg(regs.fpregs, "FIP", uint64(fpstate.__fpu_cs)<<32|uint64(fpstate.__fpu_ip))
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regs.fpregs = proc.AppendQwordReg(regs.fpregs, "FDP", uint64(fpstate.__fpu_ds)<<32|uint64(fpstate.__fpu_dp))
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for i, st := range []*C.char{&fpstate.__fpu_stmm0.__mmst_reg[0], &fpstate.__fpu_stmm1.__mmst_reg[0], &fpstate.__fpu_stmm2.__mmst_reg[0], &fpstate.__fpu_stmm3.__mmst_reg[0], &fpstate.__fpu_stmm4.__mmst_reg[0], &fpstate.__fpu_stmm5.__mmst_reg[0], &fpstate.__fpu_stmm6.__mmst_reg[0], &fpstate.__fpu_stmm7.__mmst_reg[0]} {
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stb := C.GoBytes(unsafe.Pointer(st), 10)
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mantissa := binary.LittleEndian.Uint64(stb[:8])
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exponent := binary.LittleEndian.Uint16(stb[8:])
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regs.fpregs = proc.AppendX87Reg(regs.fpregs, i, exponent, mantissa)
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}
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regs.fpregs = proc.AppendMxcsrReg(regs.fpregs, "MXCSR", uint64(fpstate.__fpu_mxcsr))
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regs.fpregs = proc.AppendDwordReg(regs.fpregs, "MXCSR_MASK", uint32(fpstate.__fpu_mxcsrmask))
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for i, xmm := range []*C.char{&fpstate.__fpu_xmm0.__xmm_reg[0], &fpstate.__fpu_xmm1.__xmm_reg[0], &fpstate.__fpu_xmm2.__xmm_reg[0], &fpstate.__fpu_xmm3.__xmm_reg[0], &fpstate.__fpu_xmm4.__xmm_reg[0], &fpstate.__fpu_xmm5.__xmm_reg[0], &fpstate.__fpu_xmm6.__xmm_reg[0], &fpstate.__fpu_xmm7.__xmm_reg[0], &fpstate.__fpu_xmm8.__xmm_reg[0], &fpstate.__fpu_xmm9.__xmm_reg[0], &fpstate.__fpu_xmm10.__xmm_reg[0], &fpstate.__fpu_xmm11.__xmm_reg[0], &fpstate.__fpu_xmm12.__xmm_reg[0], &fpstate.__fpu_xmm13.__xmm_reg[0], &fpstate.__fpu_xmm14.__xmm_reg[0], &fpstate.__fpu_xmm15.__xmm_reg[0]} {
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regs.fpregs = proc.AppendSSEReg(regs.fpregs, fmt.Sprintf("XMM%d", i), C.GoBytes(unsafe.Pointer(xmm), 16))
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}
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}
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return regs, nil
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}
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func (r *Regs) Copy() proc.Registers {
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//TODO(aarzilli): implement this to support function calls
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return nil
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}
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