7e2660e7de
The ARM64 left the vendor directory in an inconsistent state, go1.13 doesn't care so we didn't catch it but go1.14 does.
969 lines
14 KiB
Go
969 lines
14 KiB
Go
// Copyright 2017 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package arm64asm
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import (
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"fmt"
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"strings"
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)
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// An Op is an ARM64 opcode.
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type Op uint16
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// NOTE: The actual Op values are defined in tables.go.
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// They are chosen to simplify instruction decoding and
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// are not a dense packing from 0 to N, although the
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// density is high, probably at least 90%.
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func (op Op) String() string {
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if op >= Op(len(opstr)) || opstr[op] == "" {
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return fmt.Sprintf("Op(%d)", int(op))
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}
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return opstr[op]
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}
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// An Inst is a single instruction.
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type Inst struct {
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Op Op // Opcode mnemonic
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Enc uint32 // Raw encoding bits.
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Args Args // Instruction arguments, in ARM manual order.
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}
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func (i Inst) String() string {
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var args []string
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for _, arg := range i.Args {
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if arg == nil {
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break
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}
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args = append(args, arg.String())
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}
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return i.Op.String() + " " + strings.Join(args, ", ")
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}
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// An Args holds the instruction arguments.
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// If an instruction has fewer than 5 arguments,
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// the final elements in the array are nil.
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type Args [5]Arg
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// An Arg is a single instruction argument, one of these types:
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// Reg, RegSP, ImmShift, RegExtshiftAmount, PCRel, MemImmediate,
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// MemExtend, Imm, Imm64, Imm_hint, Imm_clrex, Imm_dcps, Cond,
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// Imm_c, Imm_option, Imm_prfop, Pstatefield, Systemreg, Imm_fp
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// RegisterWithArrangement, RegisterWithArrangementAndIndex.
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type Arg interface {
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isArg()
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String() string
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}
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// A Reg is a single register.
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// The zero value denotes W0, not the absence of a register.
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type Reg uint16
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const (
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W0 Reg = iota
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W1
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W2
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W3
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W4
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W5
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W6
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W7
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W8
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W9
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W10
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W11
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W12
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W13
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W14
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W15
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W16
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W17
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W18
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W19
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W20
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W21
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W22
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W23
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W24
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W25
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W26
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W27
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W28
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W29
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W30
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WZR
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X0
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X1
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X2
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X3
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X4
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X5
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X6
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X7
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X8
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X9
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X10
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X11
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X12
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X13
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X14
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X15
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X16
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X17
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X18
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X19
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X20
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X21
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X22
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X23
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X24
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X25
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X26
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X27
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X28
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X29
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X30
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XZR
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B0
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B1
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B2
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B3
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B4
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B5
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B6
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B7
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B8
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B9
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B10
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B11
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B12
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B13
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B14
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B15
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B16
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B17
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B18
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B19
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B20
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B21
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B22
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B23
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B24
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B25
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B26
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B27
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B28
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B29
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B30
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B31
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H0
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H1
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H2
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H3
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H4
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H5
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H6
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H7
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H8
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H9
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H10
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H11
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H12
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H13
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H14
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H15
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H16
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H17
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H18
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H19
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H20
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H21
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H22
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H23
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H24
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H25
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H26
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H27
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H28
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H29
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H30
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H31
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S0
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S1
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S2
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S3
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S4
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S5
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S6
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S7
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S8
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S9
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S10
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S11
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S12
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S13
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S14
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S15
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S16
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S17
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S18
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S19
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S20
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S21
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S22
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S23
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S24
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S25
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S26
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S27
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S28
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S29
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S30
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S31
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D0
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D1
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D2
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D3
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D4
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D5
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D6
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D7
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D8
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D9
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D10
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D11
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D12
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D13
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D14
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D15
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D16
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D17
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D18
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D19
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D20
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D21
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D22
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D23
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D24
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D25
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D26
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D27
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D28
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D29
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D30
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D31
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Q0
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Q1
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Q2
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Q3
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Q4
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Q5
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Q6
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Q7
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Q8
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Q9
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Q10
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Q11
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Q12
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Q13
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Q14
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Q15
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Q16
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Q17
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Q18
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Q19
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Q20
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Q21
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Q22
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Q23
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Q24
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Q25
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Q26
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Q27
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Q28
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Q29
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Q30
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Q31
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V0
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V1
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V2
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V3
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V4
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V5
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V6
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V7
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V8
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V9
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V10
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V11
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V12
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V13
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V14
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V15
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V16
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V17
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V18
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V19
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V20
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V21
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V22
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V23
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V24
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V25
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V26
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V27
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V28
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V29
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V30
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V31
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WSP = WZR // These are different registers with the same encoding.
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SP = XZR // These are different registers with the same encoding.
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)
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func (Reg) isArg() {}
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func (r Reg) String() string {
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switch {
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case r == WZR:
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return "WZR"
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case r == XZR:
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return "XZR"
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case W0 <= r && r <= W30:
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return fmt.Sprintf("W%d", int(r-W0))
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case X0 <= r && r <= X30:
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return fmt.Sprintf("X%d", int(r-X0))
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case B0 <= r && r <= B31:
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return fmt.Sprintf("B%d", int(r-B0))
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case H0 <= r && r <= H31:
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return fmt.Sprintf("H%d", int(r-H0))
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case S0 <= r && r <= S31:
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return fmt.Sprintf("S%d", int(r-S0))
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case D0 <= r && r <= D31:
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return fmt.Sprintf("D%d", int(r-D0))
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case Q0 <= r && r <= Q31:
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return fmt.Sprintf("Q%d", int(r-Q0))
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case V0 <= r && r <= V31:
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return fmt.Sprintf("V%d", int(r-V0))
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default:
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return fmt.Sprintf("Reg(%d)", int(r))
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}
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}
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// A RegSP represent a register and X31/W31 is regarded as SP/WSP.
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type RegSP Reg
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func (RegSP) isArg() {}
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func (r RegSP) String() string {
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switch Reg(r) {
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case WSP:
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return "WSP"
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case SP:
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return "SP"
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default:
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return Reg(r).String()
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}
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}
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type ImmShift struct {
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imm uint16
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shift uint8
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}
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func (ImmShift) isArg() {}
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func (is ImmShift) String() string {
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if is.shift == 0 {
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return fmt.Sprintf("#%#x", is.imm)
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}
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if is.shift < 128 {
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return fmt.Sprintf("#%#x, LSL #%d", is.imm, is.shift)
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}
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return fmt.Sprintf("#%#x, MSL #%d", is.imm, is.shift-128)
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}
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type ExtShift uint8
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const (
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_ ExtShift = iota
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uxtb
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uxth
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uxtw
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uxtx
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sxtb
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sxth
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sxtw
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sxtx
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lsl
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lsr
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asr
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ror
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)
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func (extShift ExtShift) String() string {
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switch extShift {
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case uxtb:
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return "UXTB"
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case uxth:
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return "UXTH"
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case uxtw:
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return "UXTW"
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case uxtx:
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return "UXTX"
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case sxtb:
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return "SXTB"
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case sxth:
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return "SXTH"
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case sxtw:
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return "SXTW"
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case sxtx:
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return "SXTX"
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case lsl:
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return "LSL"
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case lsr:
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return "LSR"
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case asr:
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return "ASR"
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case ror:
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return "ROR"
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}
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return ""
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}
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type RegExtshiftAmount struct {
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reg Reg
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extShift ExtShift
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amount uint8
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show_zero bool
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}
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func (RegExtshiftAmount) isArg() {}
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func (rea RegExtshiftAmount) String() string {
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buf := rea.reg.String()
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if rea.extShift != ExtShift(0) {
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buf += ", " + rea.extShift.String()
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if rea.amount != 0 {
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buf += fmt.Sprintf(" #%d", rea.amount)
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} else {
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if rea.show_zero == true {
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buf += fmt.Sprintf(" #%d", rea.amount)
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}
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}
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}
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return buf
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}
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// A PCRel describes a memory address (usually a code label)
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// as a distance relative to the program counter.
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type PCRel int64
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func (PCRel) isArg() {}
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func (r PCRel) String() string {
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return fmt.Sprintf(".%+#x", uint64(r))
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}
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// An AddrMode is an ARM addressing mode.
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type AddrMode uint8
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const (
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_ AddrMode = iota
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AddrPostIndex // [R], X - use address R, set R = R + X
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AddrPreIndex // [R, X]! - use address R + X, set R = R + X
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AddrOffset // [R, X] - use address R + X
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AddrPostReg // [Rn], Rm - - use address Rn, set Rn = Rn + Rm
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)
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// A MemImmediate is a memory reference made up of a base R and immediate X.
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// The effective memory address is R or R+X depending on AddrMode.
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type MemImmediate struct {
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Base RegSP
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Mode AddrMode
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imm int32
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}
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func (MemImmediate) isArg() {}
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func (m MemImmediate) String() string {
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R := m.Base.String()
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X := fmt.Sprintf("#%d", m.imm)
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switch m.Mode {
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case AddrOffset:
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if X == "#0" {
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return fmt.Sprintf("[%s]", R)
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}
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return fmt.Sprintf("[%s,%s]", R, X)
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case AddrPreIndex:
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return fmt.Sprintf("[%s,%s]!", R, X)
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case AddrPostIndex:
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return fmt.Sprintf("[%s],%s", R, X)
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case AddrPostReg:
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post := Reg(X0) + Reg(m.imm)
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postR := post.String()
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return fmt.Sprintf("[%s], %s", R, postR)
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}
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return fmt.Sprintf("unimplemented!")
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}
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// A MemExtend is a memory reference made up of a base R and index expression X.
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// The effective memory address is R or R+X depending on Index, Extend and Amount.
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type MemExtend struct {
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Base RegSP
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Index Reg
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Extend ExtShift
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// Amount indicates the index shift amount (but also see ShiftMustBeZero field below).
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Amount uint8
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// ShiftMustBeZero is set to true when the shift amount must be 0, even if the
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// Amount field is not 0. In GNU syntax, a #0 shift amount is printed if Amount
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// is not 0 but ShiftMustBeZero is true; #0 is not printed if Amount is 0 and
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// ShiftMustBeZero is true. Both cases represent shift by 0 bit.
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ShiftMustBeZero bool
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}
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func (MemExtend) isArg() {}
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func (m MemExtend) String() string {
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Rbase := m.Base.String()
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RIndex := m.Index.String()
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if m.ShiftMustBeZero {
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if m.Amount != 0 {
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return fmt.Sprintf("[%s,%s,%s #0]", Rbase, RIndex, m.Extend.String())
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} else {
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if m.Extend != lsl {
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return fmt.Sprintf("[%s,%s,%s]", Rbase, RIndex, m.Extend.String())
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} else {
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return fmt.Sprintf("[%s,%s]", Rbase, RIndex)
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}
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}
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} else {
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if m.Amount != 0 {
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return fmt.Sprintf("[%s,%s,%s #%d]", Rbase, RIndex, m.Extend.String(), m.Amount)
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} else {
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if m.Extend != lsl {
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return fmt.Sprintf("[%s,%s,%s]", Rbase, RIndex, m.Extend.String())
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} else {
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return fmt.Sprintf("[%s,%s]", Rbase, RIndex)
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}
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}
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}
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}
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// An Imm is an integer constant.
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type Imm struct {
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Imm uint32
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Decimal bool
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}
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func (Imm) isArg() {}
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func (i Imm) String() string {
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if !i.Decimal {
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return fmt.Sprintf("#%#x", i.Imm)
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} else {
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return fmt.Sprintf("#%d", i.Imm)
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}
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}
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type Imm64 struct {
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Imm uint64
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Decimal bool
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}
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func (Imm64) isArg() {}
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func (i Imm64) String() string {
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if !i.Decimal {
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return fmt.Sprintf("#%#x", i.Imm)
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} else {
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return fmt.Sprintf("#%d", i.Imm)
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}
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}
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// An Imm_hint is an integer constant for HINT instruction.
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type Imm_hint uint8
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func (Imm_hint) isArg() {}
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func (i Imm_hint) String() string {
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return fmt.Sprintf("#%#x", uint32(i))
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}
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// An Imm_clrex is an integer constant for CLREX instruction.
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type Imm_clrex uint8
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func (Imm_clrex) isArg() {}
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func (i Imm_clrex) String() string {
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if i == 15 {
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return ""
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}
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return fmt.Sprintf("#%#x", uint32(i))
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}
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// An Imm_dcps is an integer constant for DCPS[123] instruction.
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type Imm_dcps uint16
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func (Imm_dcps) isArg() {}
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func (i Imm_dcps) String() string {
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if i == 0 {
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return ""
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}
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return fmt.Sprintf("#%#x", uint32(i))
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}
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// Standard conditions.
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type Cond struct {
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Value uint8
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Invert bool
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}
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func (Cond) isArg() {}
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func (c Cond) String() string {
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cond31 := c.Value >> 1
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invert := bool((c.Value & 1) == 1)
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invert = (invert != c.Invert)
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switch cond31 {
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case 0:
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if invert {
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return "NE"
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} else {
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return "EQ"
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}
|
|
case 1:
|
|
if invert {
|
|
return "CC"
|
|
} else {
|
|
return "CS"
|
|
}
|
|
case 2:
|
|
if invert {
|
|
return "PL"
|
|
} else {
|
|
return "MI"
|
|
}
|
|
case 3:
|
|
if invert {
|
|
return "VC"
|
|
} else {
|
|
return "VS"
|
|
}
|
|
case 4:
|
|
if invert {
|
|
return "LS"
|
|
} else {
|
|
return "HI"
|
|
}
|
|
case 5:
|
|
if invert {
|
|
return "LT"
|
|
} else {
|
|
return "GE"
|
|
}
|
|
case 6:
|
|
if invert {
|
|
return "LE"
|
|
} else {
|
|
return "GT"
|
|
}
|
|
case 7:
|
|
return "AL"
|
|
}
|
|
return ""
|
|
}
|
|
|
|
// An Imm_c is an integer constant for SYS/SYSL/TLBI instruction.
|
|
type Imm_c uint8
|
|
|
|
func (Imm_c) isArg() {}
|
|
|
|
func (i Imm_c) String() string {
|
|
return fmt.Sprintf("C%d", uint8(i))
|
|
}
|
|
|
|
// An Imm_option is an integer constant for DMB/DSB/ISB instruction.
|
|
type Imm_option uint8
|
|
|
|
func (Imm_option) isArg() {}
|
|
|
|
func (i Imm_option) String() string {
|
|
switch uint8(i) {
|
|
case 15:
|
|
return "SY"
|
|
case 14:
|
|
return "ST"
|
|
case 13:
|
|
return "LD"
|
|
case 11:
|
|
return "ISH"
|
|
case 10:
|
|
return "ISHST"
|
|
case 9:
|
|
return "ISHLD"
|
|
case 7:
|
|
return "NSH"
|
|
case 6:
|
|
return "NSHST"
|
|
case 5:
|
|
return "NSHLD"
|
|
case 3:
|
|
return "OSH"
|
|
case 2:
|
|
return "OSHST"
|
|
case 1:
|
|
return "OSHLD"
|
|
}
|
|
return fmt.Sprintf("#%#02x", uint8(i))
|
|
}
|
|
|
|
// An Imm_prfop is an integer constant for PRFM instruction.
|
|
type Imm_prfop uint8
|
|
|
|
func (Imm_prfop) isArg() {}
|
|
|
|
func (i Imm_prfop) String() string {
|
|
prf_type := (i >> 3) & (1<<2 - 1)
|
|
prf_target := (i >> 1) & (1<<2 - 1)
|
|
prf_policy := i & 1
|
|
var result string
|
|
|
|
switch prf_type {
|
|
case 0:
|
|
result = "PLD"
|
|
case 1:
|
|
result = "PLI"
|
|
case 2:
|
|
result = "PST"
|
|
case 3:
|
|
return fmt.Sprintf("#%#02x", uint8(i))
|
|
}
|
|
switch prf_target {
|
|
case 0:
|
|
result += "L1"
|
|
case 1:
|
|
result += "L2"
|
|
case 2:
|
|
result += "L3"
|
|
case 3:
|
|
return fmt.Sprintf("#%#02x", uint8(i))
|
|
}
|
|
if prf_policy == 0 {
|
|
result += "KEEP"
|
|
} else {
|
|
result += "STRM"
|
|
}
|
|
return result
|
|
}
|
|
|
|
type Pstatefield uint8
|
|
|
|
const (
|
|
SPSel Pstatefield = iota
|
|
DAIFSet
|
|
DAIFClr
|
|
)
|
|
|
|
func (Pstatefield) isArg() {}
|
|
|
|
func (p Pstatefield) String() string {
|
|
switch p {
|
|
case SPSel:
|
|
return "SPSel"
|
|
case DAIFSet:
|
|
return "DAIFSet"
|
|
case DAIFClr:
|
|
return "DAIFClr"
|
|
default:
|
|
return "unimplemented"
|
|
}
|
|
}
|
|
|
|
type Systemreg struct {
|
|
op0 uint8
|
|
op1 uint8
|
|
cn uint8
|
|
cm uint8
|
|
op2 uint8
|
|
}
|
|
|
|
func (Systemreg) isArg() {}
|
|
|
|
func (s Systemreg) String() string {
|
|
return fmt.Sprintf("S%d_%d_C%d_C%d_%d",
|
|
s.op0, s.op1, s.cn, s.cm, s.op2)
|
|
}
|
|
|
|
// An Imm_fp is a signed floating-point constant.
|
|
type Imm_fp struct {
|
|
s uint8
|
|
exp int8
|
|
pre uint8
|
|
}
|
|
|
|
func (Imm_fp) isArg() {}
|
|
|
|
func (i Imm_fp) String() string {
|
|
var s, pre, numerator, denominator int16
|
|
var result float64
|
|
if i.s == 0 {
|
|
s = 1
|
|
} else {
|
|
s = -1
|
|
}
|
|
pre = s * int16(16+i.pre)
|
|
if i.exp > 0 {
|
|
numerator = (pre << uint8(i.exp))
|
|
denominator = 16
|
|
} else {
|
|
numerator = pre
|
|
denominator = (16 << uint8(-1*i.exp))
|
|
}
|
|
result = float64(numerator) / float64(denominator)
|
|
return fmt.Sprintf("#%.18e", result)
|
|
}
|
|
|
|
type Arrangement uint8
|
|
|
|
const (
|
|
_ Arrangement = iota
|
|
ArrangementB
|
|
Arrangement8B
|
|
Arrangement16B
|
|
ArrangementH
|
|
Arrangement4H
|
|
Arrangement8H
|
|
ArrangementS
|
|
Arrangement2S
|
|
Arrangement4S
|
|
ArrangementD
|
|
Arrangement1D
|
|
Arrangement2D
|
|
Arrangement1Q
|
|
)
|
|
|
|
func (a Arrangement) String() (result string) {
|
|
switch a {
|
|
case ArrangementB:
|
|
result = ".B"
|
|
case Arrangement8B:
|
|
result = ".8B"
|
|
case Arrangement16B:
|
|
result = ".16B"
|
|
case ArrangementH:
|
|
result = ".H"
|
|
case Arrangement4H:
|
|
result = ".4H"
|
|
case Arrangement8H:
|
|
result = ".8H"
|
|
case ArrangementS:
|
|
result = ".S"
|
|
case Arrangement2S:
|
|
result = ".2S"
|
|
case Arrangement4S:
|
|
result = ".4S"
|
|
case ArrangementD:
|
|
result = ".D"
|
|
case Arrangement1D:
|
|
result = ".1D"
|
|
case Arrangement2D:
|
|
result = ".2D"
|
|
case Arrangement1Q:
|
|
result = ".1Q"
|
|
}
|
|
return
|
|
}
|
|
|
|
// Register with arrangement: <Vd>.<T>, { <Vt>.8B, <Vt2>.8B},
|
|
type RegisterWithArrangement struct {
|
|
r Reg
|
|
a Arrangement
|
|
cnt uint8
|
|
}
|
|
|
|
func (RegisterWithArrangement) isArg() {}
|
|
|
|
func (r RegisterWithArrangement) String() string {
|
|
result := r.r.String()
|
|
result += r.a.String()
|
|
if r.cnt > 0 {
|
|
result = "{" + result
|
|
if r.cnt == 2 {
|
|
r1 := V0 + Reg((uint16(r.r)-uint16(V0)+1)&31)
|
|
result += ", " + r1.String() + r.a.String()
|
|
} else if r.cnt > 2 {
|
|
if (uint16(r.cnt) + ((uint16(r.r) - uint16(V0)) & 31)) > 32 {
|
|
for i := 1; i < int(r.cnt); i++ {
|
|
cur := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(i))&31)
|
|
result += ", " + cur.String() + r.a.String()
|
|
}
|
|
} else {
|
|
r1 := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(r.cnt)-1)&31)
|
|
result += "-" + r1.String() + r.a.String()
|
|
}
|
|
}
|
|
result += "}"
|
|
}
|
|
return result
|
|
}
|
|
|
|
// Register with arrangement and index: <Vm>.<Ts>[<index>],
|
|
// { <Vt>.B, <Vt2>.B }[<index>].
|
|
type RegisterWithArrangementAndIndex struct {
|
|
r Reg
|
|
a Arrangement
|
|
index uint8
|
|
cnt uint8
|
|
}
|
|
|
|
func (RegisterWithArrangementAndIndex) isArg() {}
|
|
|
|
func (r RegisterWithArrangementAndIndex) String() string {
|
|
result := r.r.String()
|
|
result += r.a.String()
|
|
if r.cnt > 0 {
|
|
result = "{" + result
|
|
if r.cnt == 2 {
|
|
r1 := V0 + Reg((uint16(r.r)-uint16(V0)+1)&31)
|
|
result += ", " + r1.String() + r.a.String()
|
|
} else if r.cnt > 2 {
|
|
if (uint16(r.cnt) + ((uint16(r.r) - uint16(V0)) & 31)) > 32 {
|
|
for i := 1; i < int(r.cnt); i++ {
|
|
cur := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(i))&31)
|
|
result += ", " + cur.String() + r.a.String()
|
|
}
|
|
} else {
|
|
r1 := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(r.cnt)-1)&31)
|
|
result += "-" + r1.String() + r.a.String()
|
|
}
|
|
}
|
|
result += "}"
|
|
}
|
|
return fmt.Sprintf("%s[%d]", result, r.index)
|
|
}
|