abc948b0ae
added loong64 support for gnu format disassembler and plan9 format disassembler in golang.org/x/arch $ go get -u golang.org/x/arch@v0.11.0 $ go mod tidy $ go mod vendor Co-authored-by: Huang Qiqi <huangqiqi@loongson.cn>
94 lines
2.1 KiB
Go
94 lines
2.1 KiB
Go
// Copyright 2024 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package loong64asm
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// Naming for Go decoder arguments:
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//
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// - arg_fd: a Floating Point operand register fd encoded in the fd[4:0] field
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//
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// - arg_fj: a Floating Point operand register fj encoded in the fj[9:5] field
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//
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// - arg_fk: a Floating Point operand register fk encoded in the fk[14:10] field
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//
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// - arg_fa: a Floating Point operand register fa encoded in the fa[19:15] field
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//
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// - arg_rd: a general-purpose register rd encoded in the rd[4:0] field
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//
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// - arg_rj: a general-purpose register rj encoded in the rj[9:5] field
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//
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// - arg_rk: a general-purpose register rk encoded in the rk[14:10] field
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//
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// - arg_fcsr_4_0: float control status register encoded in [4:0] field
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//
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// - arg_cd_2_0: condition flag register encoded in [2:0] field
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//
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// - arg_sa2_16_15: shift bits constant encoded in [16:15] field
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//
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// - arg_code_14_0: arg for exception process routine encoded in [14:0] field
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//
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// - arg_ui5_14_10: 5bits unsigned immediate
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//
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// - arg_lsbw: For details, please refer to chapter 2.2.3.8 of instruction manual
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//
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// - arg_msbw: For details, please refer to chapter 2.2.3.9 of instruction manual
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//
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// - arg_hint_4_0: hint field implied the prefetch type and the data should fetch to cache's level
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// 0: load to data cache level 1
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// 8: store to data cache level 1
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// other: no define
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//
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// - arg_si12_21_10: 12bits signed immediate
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type instArg uint16
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const (
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_ instArg = iota
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// 1-5
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arg_fd
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arg_fj
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arg_fk
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arg_fa
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arg_rd
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// 6-10
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arg_rj
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arg_rk
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arg_op_4_0
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arg_fcsr_4_0
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arg_fcsr_9_5
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// 11-15
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arg_csr_23_10
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arg_cd
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arg_cj
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arg_ca
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arg_sa2_16_15
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// 16-20
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arg_sa3_17_15
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arg_code_4_0
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arg_code_14_0
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arg_ui5_14_10
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arg_ui6_15_10
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// 21-25
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arg_ui12_21_10
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arg_lsbw
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arg_msbw
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arg_lsbd
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arg_msbd
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// 26-30
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arg_hint_4_0
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arg_hint_14_0
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arg_level_14_0
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arg_level_17_10
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arg_seq_17_10
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// 31-35
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arg_si12_21_10
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arg_si14_23_10
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arg_si16_25_10
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arg_si20_24_5
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arg_offset_20_0
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// 36~
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arg_offset_25_0
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arg_offset_15_0
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)
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