abc948b0ae
added loong64 support for gnu format disassembler and plan9 format disassembler in golang.org/x/arch $ go get -u golang.org/x/arch@v0.11.0 $ go mod tidy $ go mod vendor Co-authored-by: Huang Qiqi <huangqiqi@loongson.cn>
542 lines
13 KiB
Go
542 lines
13 KiB
Go
// Copyright 2024 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package loong64asm
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import (
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"fmt"
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"strings"
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)
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// GoSyntax returns the Go assembler syntax for the instruction.
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// The syntax was originally defined by Plan 9.
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// The pc is the program counter of the instruction, used for
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// expanding PC-relative addresses into absolute ones.
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// The symname function queries the symbol table for the program
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// being disassembled. Given a target address it returns the name
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// and base address of the symbol containing the target, if any;
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// otherwise it returns "", 0.
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func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string {
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if symname == nil {
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symname = func(uint64) (string, uint64) { return "", 0 }
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}
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if inst.Op == 0 && inst.Enc == 0 {
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return "WORD $0"
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} else if inst.Op == 0 {
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return "?"
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}
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var args []string
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for _, a := range inst.Args {
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if a == nil {
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break
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}
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args = append(args, plan9Arg(&inst, pc, symname, a))
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}
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var op string = plan9OpMap[inst.Op]
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if op == "" {
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op = "Unknown " + inst.Op.String()
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}
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switch inst.Op {
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case BSTRPICK_W, BSTRPICK_D, BSTRINS_W, BSTRINS_D:
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msbw, lsbw := inst.Args[2].(Uimm), inst.Args[3].(Uimm)
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if inst.Op == BSTRPICK_D && msbw.Imm == 15 && lsbw.Imm == 0 {
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op = "MOVHU"
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args = append(args[1:2], args[0:1]...)
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} else {
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args[0], args[2], args[3] = args[2], args[3], args[0]
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}
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case BCNEZ, BCEQZ:
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args = args[1:2]
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case BEQ, BNE:
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rj := inst.Args[0].(Reg)
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rd := inst.Args[1].(Reg)
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if rj == rd && inst.Op == BEQ {
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op = "JMP"
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args = args[2:]
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} else if rj == R0 {
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args = args[1:]
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} else if rd == R0 {
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args = append(args[:1], args[2:]...)
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}
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case BEQZ, BNEZ:
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if inst.Args[0].(Reg) == R0 && inst.Op == BEQ {
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op = "JMP"
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args = args[1:]
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}
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case BLT, BLTU, BGE, BGEU:
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rj := inst.Args[0].(Reg)
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rd := inst.Args[1].(Reg)
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if rj == rd && (inst.Op == BGE || inst.Op == BGEU) {
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op = "JMP"
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args = args[2:]
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} else if rj == R0 {
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switch inst.Op {
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case BGE:
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op = "BLEZ"
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case BLT:
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op = "BGTZ"
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}
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args = args[1:]
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} else if rd == R0 {
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if !strings.HasSuffix(op, "U") {
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op += "Z"
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}
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args = append(args[:1], args[2:]...)
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}
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case JIRL:
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rd := inst.Args[0].(Reg)
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rj := inst.Args[1].(Reg)
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regno := uint16(rj) & 31
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off := inst.Args[2].(OffsetSimm).Imm
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if rd == R0 && rj == R1 && off == 0 {
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return fmt.Sprintf("RET")
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} else if rd == R0 && off == 0 {
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return fmt.Sprintf("JMP (R%d)", regno)
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} else if rd == R0 {
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return fmt.Sprintf("JMP %d(R%d)", off, regno)
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}
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return fmt.Sprintf("CALL (R%d)", regno)
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case LD_B, LD_H, LD_W, LD_D, LD_BU, LD_HU, LD_WU, LL_W, LL_D,
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ST_B, ST_H, ST_W, ST_D, SC_W, SC_D, FLD_S, FLD_D, FST_S, FST_D:
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var off int32
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switch a := inst.Args[2].(type) {
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case Simm16:
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off = signumConvInt32(int32(a.Imm), a.Width)
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case Simm32:
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off = signumConvInt32(int32(a.Imm), a.Width) >> 2
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}
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Iop := strings.ToUpper(inst.Op.String())
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if strings.HasPrefix(Iop, "L") || strings.HasPrefix(Iop, "FL") {
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return fmt.Sprintf("%s %d(%s), %s", op, off, args[1], args[0])
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}
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return fmt.Sprintf("%s %s, %d(%s)", op, args[0], off, args[1])
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case LDX_B, LDX_H, LDX_W, LDX_D, LDX_BU, LDX_HU, LDX_WU, FLDX_S, FLDX_D,
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STX_B, STX_H, STX_W, STX_D, FSTX_S, FSTX_D:
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Iop := strings.ToUpper(inst.Op.String())
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if strings.HasPrefix(Iop, "L") || strings.HasPrefix(Iop, "FL") {
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return fmt.Sprintf("%s (%s)(%s), %s", op, args[1], args[2], args[0])
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}
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return fmt.Sprintf("%s %s, (%s)(%s)", op, args[0], args[1], args[2])
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case AMADD_B, AMADD_D, AMADD_DB_B, AMADD_DB_D, AMADD_DB_H, AMADD_DB_W, AMADD_H,
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AMADD_W, AMAND_D, AMAND_DB_D, AMAND_DB_W, AMAND_W, AMCAS_B, AMCAS_D, AMCAS_DB_B,
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AMCAS_DB_D, AMCAS_DB_H, AMCAS_DB_W, AMCAS_H, AMCAS_W, AMMAX_D, AMMAX_DB_D,
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AMMAX_DB_DU, AMMAX_DB_W, AMMAX_DB_WU, AMMAX_DU, AMMAX_W, AMMAX_WU, AMMIN_D,
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AMMIN_DB_D, AMMIN_DB_DU, AMMIN_DB_W, AMMIN_DB_WU, AMMIN_DU, AMMIN_W, AMMIN_WU,
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AMOR_D, AMOR_DB_D, AMOR_DB_W, AMOR_W, AMSWAP_B, AMSWAP_D, AMSWAP_DB_B, AMSWAP_DB_D,
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AMSWAP_DB_H, AMSWAP_DB_W, AMSWAP_H, AMSWAP_W, AMXOR_D, AMXOR_DB_D, AMXOR_DB_W, AMXOR_W:
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return fmt.Sprintf("%s %s, (%s), %s", op, args[1], args[2], args[0])
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default:
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// Reverse args, placing dest last
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for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 {
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args[i], args[j] = args[j], args[i]
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}
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switch len(args) { // Special use cases
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case 0, 1:
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if inst.Op != B && inst.Op != BL {
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return op
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}
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case 3:
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switch a0 := inst.Args[0].(type) {
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case Reg:
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rj := inst.Args[1].(Reg)
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if a0 == rj && a0 != R0 {
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args = args[0:2]
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}
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}
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switch inst.Op {
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case SUB_W, SUB_D, ADDI_W, ADDI_D, ORI:
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rj := inst.Args[1].(Reg)
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if rj == R0 {
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args = append(args[0:1], args[2:]...)
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if inst.Op == SUB_W {
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op = "NEGW"
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} else if inst.Op == SUB_D {
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op = "NEGV"
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} else {
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op = "MOVW"
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}
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}
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case ANDI:
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ui12 := inst.Args[2].(Uimm)
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if ui12.Imm == uint32(0xff) {
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op = "MOVBU"
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args = args[1:]
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} else if ui12.Imm == 0 && inst.Args[0].(Reg) == R0 && inst.Args[1].(Reg) == R0 {
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return "NOOP"
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}
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case SLL_W, OR:
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rk := inst.Args[2].(Reg)
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if rk == R0 {
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args = args[1:]
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if inst.Op == SLL_W {
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op = "MOVW"
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} else {
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op = "MOVV"
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}
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}
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}
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}
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}
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if args != nil {
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op += " " + strings.Join(args, ", ")
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}
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return op
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}
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func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
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// Reg: gpr[0, 31] and fpr[0, 31]
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// Fcsr: fcsr[0, 3]
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// Fcc: fcc[0, 7]
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// Uimm: unsigned integer constant
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// Simm16: si16
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// Simm32: si32
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// OffsetSimm: si32
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switch a := arg.(type) {
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case Reg:
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regenum := uint16(a)
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regno := uint16(a) & 0x1f
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// General-purpose register
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if regenum >= uint16(R0) && regenum <= uint16(R31) {
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return fmt.Sprintf("R%d", regno)
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} else { // Float point register
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return fmt.Sprintf("F%d", regno)
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}
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case Fcsr:
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regno := uint8(a) & 0x1f
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return fmt.Sprintf("FCSR%d", regno)
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case Fcc:
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regno := uint8(a) & 0x1f
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return fmt.Sprintf("FCC%d", regno)
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case Uimm:
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return fmt.Sprintf("$%d", a.Imm)
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case Simm16:
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si16 := signumConvInt32(int32(a.Imm), a.Width)
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return fmt.Sprintf("$%d", si16)
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case Simm32:
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si32 := signumConvInt32(a.Imm, a.Width)
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return fmt.Sprintf("$%d", si32)
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case OffsetSimm:
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offs := offsConvInt32(a.Imm, a.Width)
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if inst.Op == B || inst.Op == BL {
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addr := int64(pc) + int64(a.Imm)
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if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base {
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return fmt.Sprintf("%s(SB)", s)
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}
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}
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return fmt.Sprintf("%d(PC)", offs>>2)
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case SaSimm:
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return fmt.Sprintf("$%d", a)
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case CodeSimm:
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return fmt.Sprintf("$%d", a)
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}
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return strings.ToUpper(arg.String())
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}
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func signumConvInt32(imm int32, width uint8) int32 {
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active := uint32(1<<width) - 1
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signum := uint32(imm) & active
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if ((signum >> (width - 1)) & 0x1) == 1 {
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signum |= ^active
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}
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return int32(signum)
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}
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func offsConvInt32(imm int32, width uint8) int32 {
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relWidth := width + 2
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return signumConvInt32(imm, relWidth)
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}
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var plan9OpMap = map[Op]string{
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ADD_W: "ADD",
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ADD_D: "ADDV",
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SUB_W: "SUB",
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SUB_D: "SUBV",
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ADDI_W: "ADD",
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ADDI_D: "ADDV",
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LU12I_W: "LU12IW",
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LU32I_D: "LU32ID",
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LU52I_D: "LU52ID",
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SLT: "SGT",
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SLTU: "SGTU",
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SLTI: "SGT",
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SLTUI: "SGTU",
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PCADDU12I: "PCADDU12I",
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PCALAU12I: "PCALAU12I",
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AND: "AND",
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OR: "OR",
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NOR: "NOR",
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XOR: "XOR",
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ANDI: "AND",
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ORI: "OR",
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XORI: "XOR",
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MUL_W: "MUL",
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MULH_W: "MULH",
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MULH_WU: "MULHU",
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MUL_D: "MULV",
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MULH_D: "MULHV",
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MULH_DU: "MULHVU",
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DIV_W: "DIV",
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DIV_WU: "DIVU",
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DIV_D: "DIVV",
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DIV_DU: "DIVVU",
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MOD_W: "REM",
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MOD_WU: "REMU",
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MOD_D: "REMV",
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MOD_DU: "REMVU",
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SLL_W: "SLL",
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SRL_W: "SRL",
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SRA_W: "SRA",
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ROTR_W: "ROTR",
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SLL_D: "SLLV",
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SRL_D: "SRLV",
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SRA_D: "SRAV",
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ROTR_D: "ROTRV",
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SLLI_W: "SLL",
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SRLI_W: "SRL",
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SRAI_W: "SRA",
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ROTRI_W: "ROTR",
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SLLI_D: "SLLV",
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SRLI_D: "SRLV",
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SRAI_D: "SRAV",
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ROTRI_D: "ROTRV",
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EXT_W_B: "?",
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EXT_W_H: "?",
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BITREV_W: "BITREVW",
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BITREV_D: "BITREVV",
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CLO_W: "CLOW",
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CLO_D: "CLOV",
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CLZ_W: "CLZW",
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CLZ_D: "CLZV",
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CTO_W: "CTOW",
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CTO_D: "CTOV",
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CTZ_W: "CTZW",
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CTZ_D: "CTZV",
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REVB_2H: "REVB2H",
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REVB_2W: "REVB2W",
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REVB_4H: "REVB4H",
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REVB_D: "REVBV",
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BSTRPICK_W: "BSTRPICKW",
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BSTRPICK_D: "BSTRPICKV",
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BSTRINS_W: "BSTRINSW",
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BSTRINS_D: "BSTRINSV",
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MASKEQZ: "MASKEQZ",
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MASKNEZ: "MASKNEZ",
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BCNEZ: "BFPT",
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BCEQZ: "BFPF",
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BEQ: "BEQ",
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BNE: "BNE",
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BEQZ: "BEQ",
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BNEZ: "BNE",
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BLT: "BLT",
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BLTU: "BLTU",
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BGE: "BGE",
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BGEU: "BGEU",
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B: "JMP",
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BL: "CALL",
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LD_B: "MOVB",
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LD_H: "MOVH",
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LD_W: "MOVW",
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LD_D: "MOVV",
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LD_BU: "MOVBU",
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LD_HU: "MOVHU",
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LD_WU: "MOVWU",
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ST_B: "MOVB",
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ST_H: "MOVH",
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ST_W: "MOVW",
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ST_D: "MOVV",
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LDX_B: "MOVB",
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LDX_BU: "MOVBU",
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LDX_D: "MOVV",
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LDX_H: "MOVH",
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LDX_HU: "MOVHU",
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LDX_W: "MOVW",
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LDX_WU: "MOVWU",
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STX_B: "MOVB",
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STX_D: "MOVV",
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STX_H: "MOVH",
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STX_W: "MOVW",
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AMADD_B: "AMADDB",
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AMADD_D: "AMADDV",
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AMADD_DB_B: "AMADDDBB",
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AMADD_DB_D: "AMADDDBV",
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AMADD_DB_H: "AMADDDBH",
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AMADD_DB_W: "AMADDDBW",
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AMADD_H: "AMADDH",
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AMADD_W: "AMADDW",
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AMAND_D: "AMANDV",
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AMAND_DB_D: "AMANDDBV",
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AMAND_DB_W: "AMANDDBW",
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AMAND_W: "AMANDW",
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AMCAS_B: "AMCASB",
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AMCAS_D: "AMCASV",
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AMCAS_DB_B: "AMCASDBB",
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AMCAS_DB_D: "AMCASDBV",
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AMCAS_DB_H: "AMCASDBH",
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AMCAS_DB_W: "AMCASDBW",
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AMCAS_H: "AMCASH",
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AMCAS_W: "AMCASW",
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AMMAX_D: "AMMAXV",
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AMMAX_DB_D: "AMMAXDBV",
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AMMAX_DB_DU: "AMMAXDBVU",
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AMMAX_DB_W: "AMMAXDBW",
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AMMAX_DB_WU: "AMMAXDBWU",
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AMMAX_DU: "AMMAXVU",
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AMMAX_W: "AMMAXW",
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AMMAX_WU: "AMMAXWU",
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AMMIN_D: "AMMINV",
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AMMIN_DB_D: "AMMINDBV",
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AMMIN_DB_DU: "AMMINDBVU",
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AMMIN_DB_W: "AMMINDBW",
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AMMIN_DB_WU: "AMMINDBWU",
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AMMIN_DU: "AMMINVU",
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AMMIN_W: "AMMINW",
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AMMIN_WU: "AMMINWU",
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AMOR_D: "AMORV",
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AMOR_DB_D: "AMORDBV",
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AMOR_DB_W: "AMORDBW",
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AMOR_W: "AMORW",
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AMSWAP_B: "AMSWAPB",
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AMSWAP_D: "AMSWAPV",
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AMSWAP_DB_B: "AMSWAPDBB",
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AMSWAP_DB_D: "AMSWAPDBV",
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AMSWAP_DB_H: "AMSWAPDBH",
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AMSWAP_DB_W: "AMSWAPDBW",
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AMSWAP_H: "AMSWAPH",
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AMSWAP_W: "AMSWAPW",
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AMXOR_D: "AMXORV",
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AMXOR_DB_D: "AMXORDBV",
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AMXOR_DB_W: "AMXORDBW",
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AMXOR_W: "AMXORW",
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LL_W: "LL",
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LL_D: "LLV",
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SC_W: "SC",
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SC_D: "SCV",
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CRCC_W_B_W: "CRCCWBW",
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CRCC_W_D_W: "CRCCWVW",
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CRCC_W_H_W: "CRCCWHW",
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CRCC_W_W_W: "CRCCWWW",
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CRC_W_B_W: "CRCWBW",
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CRC_W_D_W: "CRCWVW",
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CRC_W_H_W: "CRCWHW",
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CRC_W_W_W: "CRCWWW",
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DBAR: "DBAR",
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SYSCALL: "SYSCALL",
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BREAK: "BREAK",
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RDTIMEL_W: "RDTIMELW",
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RDTIMEH_W: "RDTIMEHW",
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RDTIME_D: "RDTIMED",
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CPUCFG: "CPUCFG",
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// Floating-point instructions
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FADD_S: "ADDF",
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FADD_D: "ADDD",
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|
FSUB_S: "SUBF",
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FSUB_D: "SUBD",
|
|
FMUL_S: "MULF",
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FMUL_D: "MULD",
|
|
FDIV_S: "DIVF",
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FDIV_D: "DIVD",
|
|
FMSUB_S: "FMSUBF",
|
|
FMSUB_D: "FMSUBD",
|
|
FMADD_S: "FMADDF",
|
|
FMADD_D: "FMADDD",
|
|
FNMADD_S: "FNMADDF",
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FNMADD_D: "FNMADDD",
|
|
FNMSUB_S: "FNMSUBF",
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|
FNMSUB_D: "FNMSUBD",
|
|
FABS_S: "ABSF",
|
|
FABS_D: "ABSD",
|
|
FNEG_S: "NEGF",
|
|
FNEG_D: "NEGD",
|
|
FSQRT_S: "SQRTF",
|
|
FSQRT_D: "SQRTD",
|
|
FCOPYSIGN_S: "FCOPYSGF",
|
|
FCOPYSIGN_D: "FCOPYSGD",
|
|
FMAX_S: "FMAXF",
|
|
FMAX_D: "FMAXD",
|
|
FMIN_S: "FMINF",
|
|
FMIN_D: "FMIND",
|
|
FCLASS_S: "FCLASSF",
|
|
FCLASS_D: "FCLASSD",
|
|
FCMP_CEQ_S: "CMPEQF",
|
|
FCMP_CEQ_D: "CMPEQD",
|
|
FCMP_SLE_S: "CMPGEF",
|
|
FCMP_SLE_D: "CMPGED",
|
|
FCMP_SLT_S: "CMPGTF",
|
|
FCMP_SLT_D: "CMPGTD",
|
|
FCVT_D_S: "MOVFD",
|
|
FCVT_S_D: "MOVDF",
|
|
FFINT_S_W: "FFINTFW",
|
|
FFINT_S_L: "FFINTFV",
|
|
FFINT_D_W: "FFINTDW",
|
|
FFINT_D_L: "FFINTDV",
|
|
FTINTRM_L_D: "FTINTRMVD",
|
|
FTINTRM_L_S: "FTINTRMVF",
|
|
FTINTRM_W_D: "FTINTRMWD",
|
|
FTINTRM_W_S: "FTINTRMWF",
|
|
FTINTRNE_L_D: "FTINTRNEVD",
|
|
FTINTRNE_L_S: "FTINTRNEVF",
|
|
FTINTRNE_W_D: "FTINTRNEWD",
|
|
FTINTRNE_W_S: "FTINTRNEWF",
|
|
FTINTRP_L_D: "FTINTRPVD",
|
|
FTINTRP_L_S: "FTINTRPVF",
|
|
FTINTRP_W_D: "FTINTRPWD",
|
|
FTINTRP_W_S: "FTINTRPWF",
|
|
FTINTRZ_L_D: "FTINTRZVD",
|
|
FTINTRZ_L_S: "FTINTRZVF",
|
|
FTINTRZ_W_D: "FTINTRZWD",
|
|
FTINTRZ_W_S: "FTINTRZWF",
|
|
FTINT_L_D: "FTINTVD",
|
|
FTINT_L_S: "FTINTVF",
|
|
FTINT_W_D: "FTINTWD",
|
|
FTINT_W_S: "FTINTWF",
|
|
FRINT_S: "FRINTS",
|
|
FRINT_D: "FRINTD",
|
|
FMOV_S: "MOVF",
|
|
FMOV_D: "MOVD",
|
|
MOVGR2FR_W: "MOVW",
|
|
MOVGR2FR_D: "MOVV",
|
|
MOVFR2GR_S: "MOVW",
|
|
MOVFR2GR_D: "MOVV",
|
|
MOVGR2CF: "MOVV",
|
|
MOVCF2GR: "MOVV",
|
|
MOVFCSR2GR: "MOVV",
|
|
MOVGR2FCSR: "MOVV",
|
|
MOVFR2CF: "MOVV",
|
|
MOVCF2FR: "MOVV",
|
|
FLD_S: "MOVF",
|
|
FLD_D: "MOVD",
|
|
FST_S: "MOVF",
|
|
FST_D: "MOVD",
|
|
FLDX_S: "MOVF",
|
|
FLDX_D: "MOVD",
|
|
FSTX_S: "MOVF",
|
|
FSTX_D: "MOVD",
|
|
}
|