585c711ce5
If the base address isn't set then indexing and slicing will not work. Large floating point registers already had the base set but small general purpose registers did not.
86 lines
1.6 KiB
ArmAsm
86 lines
1.6 KiB
ArmAsm
TEXT ·fputestsetup(SB),$0-50
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// setup x87 stack
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FMOVD f64a+0(FP), F0
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FMOVD f64b+8(FP), F0
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FMOVD f64c+16(FP), F0
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FMOVD f64d+24(FP), F0
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FMOVF f32a+32(FP), F0
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FMOVF f32b+36(FP), F0
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FMOVF f32c+40(FP), F0
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FMOVF f32d+44(FP), F0
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// setup SSE registers
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// XMM0 = { f64b, f64a } = { 1.2, 1.1 }
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MOVLPS f64a+0(FP), X0
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MOVHPS f64b+8(FP), X0
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// XMM1 = { f64d, f64c } = { 1.4, 1.3 }
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MOVLPS f64c+16(FP), X1
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MOVHPS f64d+24(FP), X1
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// XMM2 = { f32d, f32c, f32b, f32a } = { 1.8, 1.7, 1.6, 1.5 }
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MOVQ f32a+32(FP), AX
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MOVQ AX, X2
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MOVQ f32c+40(FP), AX
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MOVQ AX, X3
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PUNPCKLQDQ X3, X2
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// XMM3 = { f64a, f64b } = { 1.1, 1.2 }
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MOVLPS f64b+8(FP), X3
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MOVHPS f64a+0(FP), X3
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// XMM4 = { f64c, f64d } = { 1.3, 1.4 }
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MOVLPS f64d+24(FP), X4
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MOVHPS f64c+16(FP), X4
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// XMM5 = { f32b, f32a, f32d, f32c } = { 1.6, 1.5, 1.8, 1.7 }
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MOVQ f32c+40(FP), AX
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MOVQ AX, X5
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MOVQ f32a+32(FP), AX
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MOVQ AX, X6
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PUNPCKLQDQ X6, X5
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// XMM6 = XMM0 + XMM1 = { f64b+f64d, f64a+f64c } = { 2.6, 2.4 }
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MOVAPS X0,X6
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ADDPD X1, X6
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// XMM7 = XMM0 + XMM3 = { f64b+f64a, f64a+f64b } = { 2.3, 2.3 }
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MOVAPS X0, X7
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ADDPD X3, X7
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// XMM8 = XMM2 + XMM5 = { f32d+f32b, f32c+f32a, f32b+f32d, f32a+f32c } = { 3.4, 3.2, 3.4, 3.2 }
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MOVAPS X2, X8
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ADDPS X5, X8
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MOVAPS X1, X9
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MOVAPS X2, X10
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MOVQ $42, AX
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CMPB avx2+48(FP), $0x0
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JE done
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//copy XMM1 to both halves of YMM11
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VPERMQ $0x44, Y1, Y11
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CMPB avx512+49(FP), $0x0
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JE done
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//copy YMM11 to both halves of ZMM12
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VSHUFF64X2 $0x44, Z11, Z11, Z12
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done:
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CMPB dobreak+50(FP), $0x0
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JE return
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BYTE $0xcc // INT 3
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return:
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RET
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TEXT ·getCPUID70(SB),$0
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MOVQ $7, AX
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MOVQ $0, CX
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CPUID
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MOVD BX, ret+0(FP)
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MOVD CX, ret+4(FP)
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RET
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