f3a191cd73
Implement debugging function for 386 on linux with reference to AMD64. There are a few remaining problems that need to be solved in another time. 1. The stacktrace of cgo are not exactly as expected. 2. Not implement `core` for now. 3. Not implement `call` for now. Can't not find `runtime·debugCallV1` or similar function in $GOROOT/src/runtime/asm_386.s. Update #20
287 lines
7.7 KiB
Go
287 lines
7.7 KiB
Go
package linutil
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import (
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"bytes"
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"encoding/binary"
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"fmt"
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"github.com/go-delve/delve/pkg/proc"
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"golang.org/x/arch/x86/x86asm"
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)
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// I386Registers implements the proc.Registers interface for the native/linux
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// backend and core/linux backends, on I386.
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type I386Registers struct {
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Regs *I386PtraceRegs
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Fpregs []proc.Register
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Fpregset *I386Xstate
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Tls uint64
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}
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// I386PtraceRegs is the struct used by the linux kernel to return the
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// general purpose registers for I386 CPUs.
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type I386PtraceRegs struct {
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Ebx int32
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Ecx int32
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Edx int32
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Esi int32
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Edi int32
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Ebp int32
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Eax int32
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Xds int32
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Xes int32
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Xfs int32
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Xgs int32
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Orig_eax int32
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Eip int32
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Xcs int32
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Eflags int32
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Esp int32
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Xss int32
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}
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// Slice returns the registers as a list of (name, value) pairs.
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func (r *I386Registers) Slice(floatingPoint bool) []proc.Register {
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var regs = []struct {
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k string
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v int32
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}{
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{"Ebx", r.Regs.Ebx},
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{"Ecx", r.Regs.Ecx},
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{"Edx", r.Regs.Edx},
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{"Esi", r.Regs.Esi},
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{"Edi", r.Regs.Edi},
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{"Ebp", r.Regs.Ebp},
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{"Eax", r.Regs.Eax},
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{"Xds", r.Regs.Xds},
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{"Xes", r.Regs.Xes},
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{"Xfs", r.Regs.Xfs},
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{"Xgs", r.Regs.Xgs},
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{"Orig_eax", r.Regs.Orig_eax},
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{"Eip", r.Regs.Eip},
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{"Xcs", r.Regs.Xcs},
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{"Eflags", r.Regs.Eflags},
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{"Esp", r.Regs.Esp},
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{"Xss", r.Regs.Xss},
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}
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out := make([]proc.Register, 0, len(regs)+len(r.Fpregs))
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for _, reg := range regs {
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out = proc.AppendUint64Register(out, reg.k, uint64(uint32(reg.v)))
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}
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if floatingPoint {
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out = append(out, r.Fpregs...)
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}
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return out
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}
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// PC returns the value of EIP register.
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func (r *I386Registers) PC() uint64 {
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return uint64(uint32(r.Regs.Eip))
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}
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// SP returns the value of ESP register.
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func (r *I386Registers) SP() uint64 {
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return uint64(uint32(r.Regs.Esp))
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}
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func (r *I386Registers) BP() uint64 {
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return uint64(uint32(r.Regs.Ebp))
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}
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// CX returns the value of ECX register.
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func (r *I386Registers) CX() uint64 {
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return uint64(uint32(r.Regs.Ecx))
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}
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// TLS returns the address of the thread local storage memory segment.
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func (r I386Registers) TLS() uint64 {
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return r.Tls
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}
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// GAddr returns the address of the G variable if it is known, 0 and false
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// otherwise.
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func (r *I386Registers) GAddr() (uint64, bool) {
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return 0, false
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}
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// Get returns the value of the n-th register (in x86asm order).
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func (r *I386Registers) Get(n int) (uint64, error) {
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reg := x86asm.Reg(n)
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const (
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mask8 = 0x000000ff
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mask16 = 0x0000ffff
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)
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switch reg {
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// 8-bit
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case x86asm.AL:
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return uint64(r.Regs.Eax) & mask8, nil
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case x86asm.CL:
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return uint64(r.Regs.Ecx) & mask8, nil
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case x86asm.DL:
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return uint64(r.Regs.Edx) & mask8, nil
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case x86asm.BL:
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return uint64(r.Regs.Ebx) & mask8, nil
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case x86asm.AH:
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return (uint64(r.Regs.Eax) >> 8) & mask8, nil
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case x86asm.CH:
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return (uint64(r.Regs.Ecx) >> 8) & mask8, nil
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case x86asm.DH:
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return (uint64(r.Regs.Edx) >> 8) & mask8, nil
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case x86asm.BH:
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return (uint64(r.Regs.Ebx) >> 8) & mask8, nil
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case x86asm.SPB:
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return uint64(r.Regs.Esp) & mask8, nil
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case x86asm.BPB:
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return uint64(r.Regs.Ebp) & mask8, nil
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case x86asm.SIB:
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return uint64(r.Regs.Esi) & mask8, nil
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case x86asm.DIB:
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return uint64(r.Regs.Edi) & mask8, nil
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// 16-bit
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case x86asm.AX:
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return uint64(r.Regs.Eax) & mask16, nil
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case x86asm.CX:
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return uint64(r.Regs.Ecx) & mask16, nil
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case x86asm.DX:
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return uint64(r.Regs.Edx) & mask16, nil
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case x86asm.BX:
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return uint64(r.Regs.Ebx) & mask16, nil
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case x86asm.SP:
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return uint64(r.Regs.Esp) & mask16, nil
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case x86asm.BP:
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return uint64(r.Regs.Ebp) & mask16, nil
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case x86asm.SI:
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return uint64(r.Regs.Esi) & mask16, nil
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case x86asm.DI:
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return uint64(r.Regs.Edi) & mask16, nil
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// 32-bit
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case x86asm.EAX:
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return uint64(uint32(r.Regs.Eax)), nil
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case x86asm.ECX:
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return uint64(uint32(r.Regs.Ecx)), nil
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case x86asm.EDX:
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return uint64(uint32(r.Regs.Edx)), nil
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case x86asm.EBX:
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return uint64(uint32(r.Regs.Ebx)), nil
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case x86asm.ESP:
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return uint64(uint32(r.Regs.Esp)), nil
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case x86asm.EBP:
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return uint64(uint32(r.Regs.Ebp)), nil
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case x86asm.ESI:
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return uint64(uint32(r.Regs.Esi)), nil
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case x86asm.EDI:
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return uint64(uint32(r.Regs.Edi)), nil
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}
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return 0, proc.ErrUnknownRegister
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}
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// Copy returns a copy of these registers that is guarenteed not to change.
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func (r *I386Registers) Copy() proc.Registers {
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var rr I386Registers
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rr.Regs = &I386PtraceRegs{}
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rr.Fpregset = &I386Xstate{}
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*(rr.Regs) = *(r.Regs)
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if r.Fpregset != nil {
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*(rr.Fpregset) = *(r.Fpregset)
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}
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if r.Fpregs != nil {
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rr.Fpregs = make([]proc.Register, len(r.Fpregs))
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copy(rr.Fpregs, r.Fpregs)
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}
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return &rr
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}
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// I386PtraceFpRegs tracks user_fpregs_struct in /usr/include/x86_64-linux-gnu/sys/user.h
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type I386PtraceFpRegs struct {
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Cwd uint16
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Swd uint16
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Ftw uint16
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Fop uint16
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Rip uint64
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Rdp uint64
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Mxcsr uint32
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MxcrMask uint32
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StSpace [32]uint32
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XmmSpace [256]byte
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Padding [24]uint32
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}
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// I386Xstate represents amd64 XSAVE area. See Section 13.1 (and
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// following) of Intel® 64 and IA-32 Architectures Software Developer’s
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// Manual, Volume 1: Basic Architecture.
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type I386Xstate struct {
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I386PtraceFpRegs
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Xsave []byte // raw xsave area
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AvxState bool // contains AVX state
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YmmSpace [256]byte
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}
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// Decode decodes an XSAVE area to a list of name/value pairs of registers.
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func (xsave *I386Xstate) Decode() (regs []proc.Register) {
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// x87 registers
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regs = proc.AppendUint64Register(regs, "CW", uint64(xsave.Cwd))
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regs = proc.AppendUint64Register(regs, "SW", uint64(xsave.Swd))
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regs = proc.AppendUint64Register(regs, "TW", uint64(xsave.Ftw))
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regs = proc.AppendUint64Register(regs, "FOP", uint64(xsave.Fop))
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regs = proc.AppendUint64Register(regs, "FIP", uint64(xsave.Rip))
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regs = proc.AppendUint64Register(regs, "FDP", uint64(xsave.Rdp))
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for i := 0; i < len(xsave.StSpace); i += 4 {
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var buf bytes.Buffer
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binary.Write(&buf, binary.LittleEndian, uint64(xsave.StSpace[i+1])<<32|uint64(xsave.StSpace[i]))
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binary.Write(&buf, binary.LittleEndian, uint16(xsave.StSpace[i+2]))
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("ST(%d)", i/4), buf.Bytes())
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}
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// SSE registers
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regs = proc.AppendUint64Register(regs, "MXCSR", uint64(xsave.Mxcsr))
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regs = proc.AppendUint64Register(regs, "MXCSR_MASK", uint64(xsave.MxcrMask))
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for i := 0; i < len(xsave.XmmSpace); i += 16 {
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("XMM%d", i/16), xsave.XmmSpace[i:i+16])
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if xsave.AvxState {
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regs = proc.AppendBytesRegister(regs, fmt.Sprintf("YMM%d", i/16), xsave.YmmSpace[i:i+16])
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}
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}
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return
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}
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// LinuxX86XstateRead reads a byte array containing an XSAVE area into regset.
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// If readLegacy is true regset.PtraceFpRegs will be filled with the
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// contents of the legacy region of the XSAVE area.
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// See Section 13.1 (and following) of Intel® 64 and IA-32 Architectures
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// Software Developer’s Manual, Volume 1: Basic Architecture.
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func I386XstateRead(xstateargs []byte, readLegacy bool, regset *I386Xstate) error {
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if _XSAVE_HEADER_START+_XSAVE_HEADER_LEN >= len(xstateargs) {
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return nil
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}
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if readLegacy {
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rdr := bytes.NewReader(xstateargs[:_XSAVE_HEADER_START])
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if err := binary.Read(rdr, binary.LittleEndian, ®set.I386PtraceFpRegs); err != nil {
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return err
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}
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}
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xsaveheader := xstateargs[_XSAVE_HEADER_START : _XSAVE_HEADER_START+_XSAVE_HEADER_LEN]
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xstate_bv := binary.LittleEndian.Uint64(xsaveheader[0:8])
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xcomp_bv := binary.LittleEndian.Uint64(xsaveheader[8:16])
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if xcomp_bv&(1<<63) != 0 {
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// compact format not supported
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return nil
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}
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if xstate_bv&(1<<2) == 0 {
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// AVX state not present
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return nil
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}
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avxstate := xstateargs[_XSAVE_EXTENDED_REGION_START:]
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regset.AvxState = true
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copy(regset.YmmSpace[:], avxstate[:len(regset.YmmSpace)])
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return nil
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}
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