all: update golang.org/x/arch to v0.11.0 (#3826)

added loong64 support for gnu format disassembler and plan9 format disassembler in golang.org/x/arch

$ go get -u golang.org/x/arch@v0.11.0
$ go mod tidy
$ go mod vendor

Co-authored-by: Huang Qiqi <huangqiqi@loongson.cn>

go.mod

@@ -16,7 +16,7 @@ require (
 	github.com/spf13/cobra v1.7.0
 	github.com/spf13/pflag v1.0.5
 	go.starlark.net v0.0.0-20231101134539-556fd59b42f6
-	golang.org/x/arch v0.6.0
+	golang.org/x/arch v0.11.0
 	golang.org/x/sys v0.17.0
 	golang.org/x/tools v0.14.0
 	gopkg.in/yaml.v3 v3.0.1

go.sum

@@ -55,8 +55,8 @@ github.com/stretchr/testify v1.8.4 h1:CcVxjf3Q8PM0mHUKJCdn+eZZtm5yQwehR5yeSVQQcU
 github.com/stretchr/testify v1.8.4/go.mod h1:sz/lmYIOXD/1dqDmKjjqLyZ2RngseejIcXlSw2iwfAo=
 go.starlark.net v0.0.0-20231101134539-556fd59b42f6 h1:+eC0F/k4aBLC4szgOcjd7bDTEnpxADJyWJE0yowgM3E=
 go.starlark.net v0.0.0-20231101134539-556fd59b42f6/go.mod h1:LcLNIzVOMp4oV+uusnpk+VU+SzXaJakUuBjoCSWH5dM=
-golang.org/x/arch v0.6.0 h1:S0JTfE48HbRj80+4tbvZDYsJ3tGv6BUU3XxyZ7CirAc=
-golang.org/x/arch v0.6.0/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys=
+golang.org/x/arch v0.11.0 h1:KXV8WWKCXm6tRpLirl2szsO5j/oOODwZf4hATmGVNs4=
+golang.org/x/arch v0.11.0/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys=
 golang.org/x/exp v0.0.0-20230224173230-c95f2b4c22f2 h1:Jvc7gsqn21cJHCmAWx0LiimpP18LZmUxkT5Mp7EZ1mI=
 golang.org/x/exp v0.0.0-20230224173230-c95f2b4c22f2/go.mod h1:CxIveKay+FTh1D0yPZemJVgC/95VzuuOLq5Qi4xnoYc=
 golang.org/x/mod v0.14.0 h1:dGoOF9QVLYng8IHTm7BAyWqCqSheQ5pYWGhzW00YJr0=

vendor/golang.org/x/arch/LICENSE

@@ -1,4 +1,4 @@
-Copyright (c) 2015 The Go Authors. All rights reserved.
+Copyright 2015 The Go Authors.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are
@@ -10,7 +10,7 @@ notice, this list of conditions and the following disclaimer.
 copyright notice, this list of conditions and the following disclaimer
 in the documentation and/or other materials provided with the
 distribution.
-   * Neither the name of Google Inc. nor the names of its
+   * Neither the name of Google LLC nor the names of its
 contributors may be used to endorse or promote products derived from
 this software without specific prior written permission.
 

vendor/golang.org/x/arch/loong64/loong64asm/arg.go

@@ -0,0 +1,93 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package loong64asm
+
+// Naming for Go decoder arguments:
+//
+// - arg_fd: a Floating Point operand register fd encoded in the fd[4:0] field
+//
+// - arg_fj: a Floating Point operand register fj encoded in the fj[9:5] field
+//
+// - arg_fk: a Floating Point operand register fk encoded in the fk[14:10] field
+//
+// - arg_fa: a Floating Point operand register fa encoded in the fa[19:15] field
+//
+// - arg_rd: a general-purpose register rd encoded in the rd[4:0] field
+//
+// - arg_rj: a general-purpose register rj encoded in the rj[9:5] field
+//
+// - arg_rk: a general-purpose register rk encoded in the rk[14:10] field
+//
+// - arg_fcsr_4_0: float control status register encoded in [4:0] field
+//
+// - arg_cd_2_0: condition flag register encoded in [2:0] field
+//
+// - arg_sa2_16_15: shift bits constant encoded in [16:15] field
+//
+// - arg_code_14_0: arg for exception process routine encoded in [14:0] field
+//
+// - arg_ui5_14_10: 5bits unsigned immediate
+//
+// - arg_lsbw: For details, please refer to chapter 2.2.3.8 of instruction manual
+//
+// - arg_msbw: For details, please refer to chapter 2.2.3.9 of instruction manual
+//
+// - arg_hint_4_0: hint field implied the prefetch type and the data should fetch to cache's level
+//		0: load to data cache level 1
+//		8: store to data cache level 1
+//		other: no define
+//
+// - arg_si12_21_10: 12bits signed immediate
+
+type instArg uint16
+
+const (
+	_ instArg = iota
+	// 1-5
+	arg_fd
+	arg_fj
+	arg_fk
+	arg_fa
+	arg_rd
+	// 6-10
+	arg_rj
+	arg_rk
+	arg_op_4_0
+	arg_fcsr_4_0
+	arg_fcsr_9_5
+	// 11-15
+	arg_csr_23_10
+	arg_cd
+	arg_cj
+	arg_ca
+	arg_sa2_16_15
+	// 16-20
+	arg_sa3_17_15
+	arg_code_4_0
+	arg_code_14_0
+	arg_ui5_14_10
+	arg_ui6_15_10
+	// 21-25
+	arg_ui12_21_10
+	arg_lsbw
+	arg_msbw
+	arg_lsbd
+	arg_msbd
+	// 26-30
+	arg_hint_4_0
+	arg_hint_14_0
+	arg_level_14_0
+	arg_level_17_10
+	arg_seq_17_10
+	// 31-35
+	arg_si12_21_10
+	arg_si14_23_10
+	arg_si16_25_10
+	arg_si20_24_5
+	arg_offset_20_0
+	// 36~
+	arg_offset_25_0
+	arg_offset_15_0
+)

vendor/golang.org/x/arch/loong64/loong64asm/decode.go

@@ -0,0 +1,269 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package loong64asm
+
+import (
+	"encoding/binary"
+	"fmt"
+)
+
+type instArgs [5]instArg
+
+// An instFormat describes the format of an instruction encoding.
+type instFormat struct {
+	mask  uint32
+	value uint32
+	op    Op
+	// args describe how to decode the instruction arguments.
+	// args is stored as a fixed-size array.
+	// if there are fewer than len(args) arguments, args[i] == 0 marks
+	// the end of the argument list.
+	args instArgs
+}
+
+var (
+	errShort   = fmt.Errorf("truncated instruction")
+	errUnknown = fmt.Errorf("unknown instruction")
+)
+
+var decoderCover []bool
+
+func init() {
+	decoderCover = make([]bool, len(instFormats))
+}
+
+// Decode decodes the 4 bytes in src as a single instruction.
+func Decode(src []byte) (inst Inst, err error) {
+	if len(src) < 4 {
+		return Inst{}, errShort
+	}
+
+	x := binary.LittleEndian.Uint32(src)
+
+Search:
+	for i := range instFormats {
+		f := &instFormats[i]
+
+		if (x & f.mask) != f.value {
+			continue
+		}
+
+		// Decode args.
+		var args Args
+		for j, aop := range f.args {
+			if aop == 0 {
+				break
+			}
+
+			arg := decodeArg(aop, x, i)
+			if arg == nil {
+				// Cannot decode argument
+				continue Search
+			}
+
+			args[j] = arg
+		}
+
+		decoderCover[i] = true
+		inst = Inst{
+			Op:   f.op,
+			Args: args,
+			Enc:  x,
+		}
+		return inst, nil
+	}
+
+	return Inst{}, errUnknown
+}
+
+// decodeArg decodes the arg described by aop from the instruction bits x.
+// It returns nil if x cannot be decoded according to aop.
+func decodeArg(aop instArg, x uint32, index int) Arg {
+	switch aop {
+	case arg_fd:
+		return F0 + Reg(x&((1<<5)-1))
+
+	case arg_fj:
+		return F0 + Reg((x>>5)&((1<<5)-1))
+
+	case arg_fk:
+		return F0 + Reg((x>>10)&((1<<5)-1))
+
+	case arg_fa:
+		return F0 + Reg((x>>15)&((1<<5)-1))
+
+	case arg_rd:
+		return R0 + Reg(x&((1<<5)-1))
+
+	case arg_rj:
+		return R0 + Reg((x>>5)&((1<<5)-1))
+
+	case arg_rk:
+		return R0 + Reg((x>>10)&((1<<5)-1))
+
+	case arg_fcsr_4_0:
+		return FCSR0 + Fcsr(x&((1<<5)-1))
+
+	case arg_fcsr_9_5:
+		return FCSR0 + Fcsr((x>>5)&((1<<5)-1))
+
+	case arg_cd:
+		return FCC0 + Fcc(x&((1<<3)-1))
+
+	case arg_cj:
+		return FCC0 + Fcc((x>>5)&((1<<3)-1))
+
+	case arg_ca:
+		return FCC0 + Fcc((x>>15)&((1<<3)-1))
+
+	case arg_op_4_0:
+		tmp := x & ((1 << 5) - 1)
+		return Uimm{tmp, false}
+
+	case arg_csr_23_10:
+		tmp := (x >> 10) & ((1 << 14) - 1)
+		return Uimm{tmp, false}
+
+	case arg_sa2_16_15:
+		f := &instFormats[index]
+		tmp := SaSimm((x >> 15) & ((1 << 2) - 1))
+		if (f.op == ALSL_D) || (f.op == ALSL_W) || (f.op == ALSL_WU) {
+			return tmp + 1
+		} else {
+			return tmp + 0
+		}
+
+	case arg_sa3_17_15:
+		return SaSimm((x >> 15) & ((1 << 3) - 1))
+
+	case arg_code_4_0:
+		return CodeSimm(x & ((1 << 5) - 1))
+
+	case arg_code_14_0:
+		return CodeSimm(x & ((1 << 15) - 1))
+
+	case arg_ui5_14_10:
+		tmp := (x >> 10) & ((1 << 5) - 1)
+		return Uimm{tmp, false}
+
+	case arg_ui6_15_10:
+		tmp := (x >> 10) & ((1 << 6) - 1)
+		return Uimm{tmp, false}
+
+	case arg_ui12_21_10:
+		tmp := ((x >> 10) & ((1 << 12) - 1) & 0xfff)
+		return Uimm{tmp, false}
+
+	case arg_lsbw:
+		tmp := (x >> 10) & ((1 << 5) - 1)
+		return Uimm{tmp, false}
+
+	case arg_msbw:
+		tmp := (x >> 16) & ((1 << 5) - 1)
+		return Uimm{tmp, false}
+
+	case arg_lsbd:
+		tmp := (x >> 10) & ((1 << 6) - 1)
+		return Uimm{tmp, false}
+
+	case arg_msbd:
+		tmp := (x >> 16) & ((1 << 6) - 1)
+		return Uimm{tmp, false}
+
+	case arg_hint_4_0:
+		tmp := x & ((1 << 5) - 1)
+		return Uimm{tmp, false}
+
+	case arg_hint_14_0:
+		tmp := x & ((1 << 15) - 1)
+		return Uimm{tmp, false}
+
+	case arg_level_14_0:
+		tmp := x & ((1 << 15) - 1)
+		return Uimm{tmp, false}
+
+	case arg_level_17_10:
+		tmp := (x >> 10) & ((1 << 8) - 1)
+		return Uimm{tmp, false}
+
+	case arg_seq_17_10:
+		tmp := (x >> 10) & ((1 << 8) - 1)
+		return Uimm{tmp, false}
+
+	case arg_si12_21_10:
+		var tmp int16
+
+		// no int12, so sign-extend a 12-bit signed to 16-bit signed
+		if (x & 0x200000) == 0x200000 {
+			tmp = int16(((x >> 10) & ((1 << 12) - 1)) | 0xf000)
+		} else {
+			tmp = int16(((x >> 10) & ((1 << 12) - 1)) | 0x0000)
+		}
+		return Simm16{tmp, 12}
+
+	case arg_si14_23_10:
+		var tmp int32
+		if (x & 0x800000) == 0x800000 {
+			tmp = int32((((x >> 10) & ((1 << 14) - 1)) << 2) | 0xffff0000)
+		} else {
+			tmp = int32((((x >> 10) & ((1 << 14) - 1)) << 2) | 0x00000000)
+		}
+		return Simm32{tmp, 14}
+
+	case arg_si16_25_10:
+		var tmp int32
+
+		if (x & 0x2000000) == 0x2000000 {
+			tmp = int32(((x >> 10) & ((1 << 16) - 1)) | 0xffff0000)
+		} else {
+			tmp = int32(((x >> 10) & ((1 << 16) - 1)) | 0x00000000)
+		}
+
+		return Simm32{tmp, 16}
+
+	case arg_si20_24_5:
+		var tmp int32
+		if (x & 0x1000000) == 0x1000000 {
+			tmp = int32(((x >> 5) & ((1 << 20) - 1)) | 0xfff00000)
+		} else {
+			tmp = int32(((x >> 5) & ((1 << 20) - 1)) | 0x00000000)
+		}
+		return Simm32{tmp, 20}
+
+	case arg_offset_20_0:
+		var tmp int32
+
+		if (x & 0x10) == 0x10 {
+			tmp = int32(((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 21) - 1)) << 2) | 0xff800000)
+		} else {
+			tmp = int32((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 21) - 1)) << 2)
+		}
+
+		return OffsetSimm{tmp, 21}
+
+	case arg_offset_15_0:
+		var tmp int32
+		if (x & 0x2000000) == 0x2000000 {
+			tmp = int32((((x >> 10) & ((1 << 16) - 1)) << 2) | 0xfffc0000)
+		} else {
+			tmp = int32((((x >> 10) & ((1 << 16) - 1)) << 2) | 0x00000000)
+		}
+
+		return OffsetSimm{tmp, 16}
+
+	case arg_offset_25_0:
+		var tmp int32
+
+		if (x & 0x200) == 0x200 {
+			tmp = int32(((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 26) - 1)) << 2) | 0xf0000000)
+		} else {
+			tmp = int32(((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 26) - 1)) << 2) | 0x00000000)
+		}
+
+		return OffsetSimm{tmp, 26}
+	default:
+		return nil
+	}
+}

vendor/golang.org/x/arch/loong64/loong64asm/gnu.go

@@ -0,0 +1,16 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package loong64asm
+
+import (
+	"strings"
+)
+
+// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils.
+// This form typically matches the syntax defined in the Loong64 Reference Manual. See
+// https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
+func GNUSyntax(inst Inst) string {
+	return strings.ToLower(inst.String())
+}

vendor/golang.org/x/arch/loong64/loong64asm/inst.go

@@ -0,0 +1,300 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package loong64asm
+
+import (
+	"fmt"
+	"strings"
+)
+
+// An Inst is a single instruction.
+type Inst struct {
+	Op   Op     // Opcode mnemonic
+	Enc  uint32 // Raw encoding bits.
+	Args Args   // Instruction arguments, in Loong64 manual order.
+}
+
+func (i Inst) String() string {
+	var op string = i.Op.String()
+	var args []string
+
+	for _, arg := range i.Args {
+		if arg == nil {
+			break
+		}
+		args = append(args, arg.String())
+	}
+
+	switch i.Op {
+	case OR:
+		if i.Args[2].(Reg) == R0 {
+			op = "move"
+			args = args[0:2]
+		}
+
+	case ANDI:
+		if i.Args[0].(Reg) == R0 && i.Args[1].(Reg) == R0 {
+			return "nop"
+		}
+
+	case JIRL:
+		if i.Args[0].(Reg) == R0 && i.Args[1].(Reg) == R1 && i.Args[2].(OffsetSimm).Imm == 0 {
+			return "ret"
+		} else if i.Args[0].(Reg) == R0 && i.Args[2].(OffsetSimm).Imm == 0 {
+			return "jr " + args[1]
+		}
+
+	case BLT:
+		if i.Args[0].(Reg) == R0 {
+			op = "bgtz"
+			args = args[1:]
+		} else if i.Args[1].(Reg) == R0 {
+			op = "bltz"
+			args = append(args[:1], args[2:]...)
+		}
+
+	case BGE:
+		if i.Args[0].(Reg) == R0 {
+			op = "blez"
+			args = args[1:]
+		} else if i.Args[1].(Reg) == R0 {
+			op = "bgez"
+			args = append(args[:1], args[2:]...)
+		}
+	}
+
+	if len(args) == 0 {
+		return op
+	} else {
+		return op + " " + strings.Join(args, ", ")
+	}
+}
+
+// An Op is an Loong64 opcode.
+type Op uint16
+
+// NOTE: The actual Op values are defined in tables.go.
+// They are chosen to simplify instruction decoding and
+// are not a dense packing from 0 to N, although the
+// density is high, probably at least 90%.
+func (op Op) String() string {
+	if (op >= Op(len(opstr))) || (opstr[op] == "") {
+		return fmt.Sprintf("Op(%d)", int(op))
+	}
+
+	return opstr[op]
+}
+
+// An Args holds the instruction arguments.
+// If an instruction has fewer than 5 arguments,
+// the final elements in the array are nil.
+type Args [5]Arg
+
+// An Arg is a single instruction argument
+type Arg interface {
+	String() string
+}
+
+// A Reg is a single register.
+// The zero value denotes R0, not the absence of a register.
+type Reg uint16
+
+const (
+	// General-purpose register
+	R0 Reg = iota
+	R1
+	R2
+	R3
+	R4
+	R5
+	R6
+	R7
+	R8
+	R9
+	R10
+	R11
+	R12
+	R13
+	R14
+	R15
+	R16
+	R17
+	R18
+	R19
+	R20
+	R21
+	R22
+	R23
+	R24
+	R25
+	R26
+	R27
+	R28
+	R29
+	R30
+	R31
+
+	// Float point register
+	F0
+	F1
+	F2
+	F3
+	F4
+	F5
+	F6
+	F7
+	F8
+	F9
+	F10
+	F11
+	F12
+	F13
+	F14
+	F15
+	F16
+	F17
+	F18
+	F19
+	F20
+	F21
+	F22
+	F23
+	F24
+	F25
+	F26
+	F27
+	F28
+	F29
+	F30
+	F31
+)
+
+func (r Reg) String() string {
+	switch {
+	case r == R0:
+		return "$zero"
+
+	case r == R1:
+		return "$ra"
+
+	case r == R2:
+		return "$tp"
+
+	case r == R3:
+		return "$sp"
+
+	case (r >= R4) && (r <= R11):
+		return fmt.Sprintf("$a%d", int(r-R4))
+
+	case (r >= R12) && (r <= R20):
+		return fmt.Sprintf("$t%d", int(r-R12))
+
+	case r == R21:
+		return "$r21"
+
+	case r == R22:
+		return "$fp"
+
+	case (r >= R23) && (r <= R31):
+		return fmt.Sprintf("$s%d", int(r-R23))
+
+	case (r >= F0) && (r <= F7):
+		return fmt.Sprintf("$fa%d", int(r-F0))
+
+	case (r >= F8) && (r <= F23):
+		return fmt.Sprintf("$ft%d", int(r-F8))
+
+	case (r >= F24) && (r <= F31):
+		return fmt.Sprintf("$fs%d", int(r-F24))
+
+	default:
+		return fmt.Sprintf("Unknown(%d)", int(r))
+	}
+}
+
+// float control status register
+type Fcsr uint8
+
+const (
+	FCSR0 Fcsr = iota
+	FCSR1
+	FCSR2
+	FCSR3
+)
+
+func (f Fcsr) String() string {
+	return fmt.Sprintf("$fcsr%d", uint8(f))
+}
+
+// float condition flags register
+type Fcc uint8
+
+const (
+	FCC0 Fcc = iota
+	FCC1
+	FCC2
+	FCC3
+	FCC4
+	FCC5
+	FCC6
+	FCC7
+)
+
+func (f Fcc) String() string {
+	return fmt.Sprintf("$fcc%d", uint8(f))
+}
+
+// An Imm is an integer constant.
+type Uimm struct {
+	Imm     uint32
+	Decimal bool
+}
+
+func (i Uimm) String() string {
+	if i.Decimal == true {
+		return fmt.Sprintf("%d", i.Imm)
+	} else {
+		return fmt.Sprintf("%#x", i.Imm)
+	}
+}
+
+type Simm16 struct {
+	Imm   int16
+	Width uint8
+}
+
+func (si Simm16) String() string {
+	return fmt.Sprintf("%d", int32(si.Imm))
+}
+
+type Simm32 struct {
+	Imm   int32
+	Width uint8
+}
+
+func (si Simm32) String() string {
+	return fmt.Sprintf("%d", int32(si.Imm))
+}
+
+type OffsetSimm struct {
+	Imm   int32
+	Width uint8
+}
+
+func (o OffsetSimm) String() string {
+	return fmt.Sprintf("%d", int32(o.Imm))
+}
+
+type SaSimm int16
+
+func (s SaSimm) String() string {
+	return fmt.Sprintf("%#x", int(s))
+}
+
+type CodeSimm int16
+
+func (c CodeSimm) String() string {
+	return fmt.Sprintf("%#x", int(c))
+}

vendor/golang.org/x/arch/loong64/loong64asm/plan9x.go

@@ -0,0 +1,541 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package loong64asm
+
+import (
+	"fmt"
+	"strings"
+)
+
+// GoSyntax returns the Go assembler syntax for the instruction.
+// The syntax was originally defined by Plan 9.
+// The pc is the program counter of the instruction, used for
+// expanding PC-relative addresses into absolute ones.
+// The symname function queries the symbol table for the program
+// being disassembled. Given a target address it returns the name
+// and base address of the symbol containing the target, if any;
+// otherwise it returns "", 0.
+func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string {
+	if symname == nil {
+		symname = func(uint64) (string, uint64) { return "", 0 }
+	}
+	if inst.Op == 0 && inst.Enc == 0 {
+		return "WORD $0"
+	} else if inst.Op == 0 {
+		return "?"
+	}
+
+	var args []string
+	for _, a := range inst.Args {
+		if a == nil {
+			break
+		}
+		args = append(args, plan9Arg(&inst, pc, symname, a))
+	}
+
+	var op string = plan9OpMap[inst.Op]
+	if op == "" {
+		op = "Unknown " + inst.Op.String()
+	}
+
+	switch inst.Op {
+	case BSTRPICK_W, BSTRPICK_D, BSTRINS_W, BSTRINS_D:
+		msbw, lsbw := inst.Args[2].(Uimm), inst.Args[3].(Uimm)
+		if inst.Op == BSTRPICK_D && msbw.Imm == 15 && lsbw.Imm == 0 {
+			op = "MOVHU"
+			args = append(args[1:2], args[0:1]...)
+		} else {
+			args[0], args[2], args[3] = args[2], args[3], args[0]
+		}
+
+	case BCNEZ, BCEQZ:
+		args = args[1:2]
+
+	case BEQ, BNE:
+		rj := inst.Args[0].(Reg)
+		rd := inst.Args[1].(Reg)
+		if rj == rd && inst.Op == BEQ {
+			op = "JMP"
+			args = args[2:]
+		} else if rj == R0 {
+			args = args[1:]
+		} else if rd == R0 {
+			args = append(args[:1], args[2:]...)
+		}
+
+	case BEQZ, BNEZ:
+		if inst.Args[0].(Reg) == R0 && inst.Op == BEQ {
+			op = "JMP"
+			args = args[1:]
+		}
+
+	case BLT, BLTU, BGE, BGEU:
+		rj := inst.Args[0].(Reg)
+		rd := inst.Args[1].(Reg)
+		if rj == rd && (inst.Op == BGE || inst.Op == BGEU) {
+			op = "JMP"
+			args = args[2:]
+		} else if rj == R0 {
+			switch inst.Op {
+			case BGE:
+				op = "BLEZ"
+			case BLT:
+				op = "BGTZ"
+			}
+			args = args[1:]
+		} else if rd == R0 {
+			if !strings.HasSuffix(op, "U") {
+				op += "Z"
+			}
+			args = append(args[:1], args[2:]...)
+		}
+
+	case JIRL:
+		rd := inst.Args[0].(Reg)
+		rj := inst.Args[1].(Reg)
+		regno := uint16(rj) & 31
+		off := inst.Args[2].(OffsetSimm).Imm
+		if rd == R0 && rj == R1 && off == 0 {
+			return fmt.Sprintf("RET")
+		} else if rd == R0 && off == 0 {
+			return fmt.Sprintf("JMP (R%d)", regno)
+		} else if rd == R0 {
+			return fmt.Sprintf("JMP %d(R%d)", off, regno)
+		}
+		return fmt.Sprintf("CALL (R%d)", regno)
+
+	case LD_B, LD_H, LD_W, LD_D, LD_BU, LD_HU, LD_WU, LL_W, LL_D,
+		ST_B, ST_H, ST_W, ST_D, SC_W, SC_D, FLD_S, FLD_D, FST_S, FST_D:
+		var off int32
+		switch a := inst.Args[2].(type) {
+		case Simm16:
+			off = signumConvInt32(int32(a.Imm), a.Width)
+		case Simm32:
+			off = signumConvInt32(int32(a.Imm), a.Width) >> 2
+		}
+		Iop := strings.ToUpper(inst.Op.String())
+		if strings.HasPrefix(Iop, "L") || strings.HasPrefix(Iop, "FL") {
+			return fmt.Sprintf("%s %d(%s), %s", op, off, args[1], args[0])
+		}
+		return fmt.Sprintf("%s %s, %d(%s)", op, args[0], off, args[1])
+
+	case LDX_B, LDX_H, LDX_W, LDX_D, LDX_BU, LDX_HU, LDX_WU, FLDX_S, FLDX_D,
+		STX_B, STX_H, STX_W, STX_D, FSTX_S, FSTX_D:
+		Iop := strings.ToUpper(inst.Op.String())
+		if strings.HasPrefix(Iop, "L") || strings.HasPrefix(Iop, "FL") {
+			return fmt.Sprintf("%s (%s)(%s), %s", op, args[1], args[2], args[0])
+		}
+		return fmt.Sprintf("%s %s, (%s)(%s)", op, args[0], args[1], args[2])
+
+	case AMADD_B, AMADD_D, AMADD_DB_B, AMADD_DB_D, AMADD_DB_H, AMADD_DB_W, AMADD_H,
+		AMADD_W, AMAND_D, AMAND_DB_D, AMAND_DB_W, AMAND_W, AMCAS_B, AMCAS_D, AMCAS_DB_B,
+		AMCAS_DB_D, AMCAS_DB_H, AMCAS_DB_W, AMCAS_H, AMCAS_W, AMMAX_D, AMMAX_DB_D,
+		AMMAX_DB_DU, AMMAX_DB_W, AMMAX_DB_WU, AMMAX_DU, AMMAX_W, AMMAX_WU, AMMIN_D,
+		AMMIN_DB_D, AMMIN_DB_DU, AMMIN_DB_W, AMMIN_DB_WU, AMMIN_DU, AMMIN_W, AMMIN_WU,
+		AMOR_D, AMOR_DB_D, AMOR_DB_W, AMOR_W, AMSWAP_B, AMSWAP_D, AMSWAP_DB_B, AMSWAP_DB_D,
+		AMSWAP_DB_H, AMSWAP_DB_W, AMSWAP_H, AMSWAP_W, AMXOR_D, AMXOR_DB_D, AMXOR_DB_W, AMXOR_W:
+		return fmt.Sprintf("%s %s, (%s), %s", op, args[1], args[2], args[0])
+
+	default:
+		// Reverse args, placing dest last
+		for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 {
+			args[i], args[j] = args[j], args[i]
+		}
+		switch len(args) { // Special use cases
+		case 0, 1:
+			if inst.Op != B && inst.Op != BL {
+				return op
+			}
+
+		case 3:
+			switch a0 := inst.Args[0].(type) {
+			case Reg:
+				rj := inst.Args[1].(Reg)
+				if a0 == rj && a0 != R0 {
+					args = args[0:2]
+				}
+			}
+			switch inst.Op {
+			case SUB_W, SUB_D, ADDI_W, ADDI_D, ORI:
+				rj := inst.Args[1].(Reg)
+				if rj == R0 {
+					args = append(args[0:1], args[2:]...)
+					if inst.Op == SUB_W {
+						op = "NEGW"
+					} else if inst.Op == SUB_D {
+						op = "NEGV"
+					} else {
+						op = "MOVW"
+					}
+				}
+
+			case ANDI:
+				ui12 := inst.Args[2].(Uimm)
+				if ui12.Imm == uint32(0xff) {
+					op = "MOVBU"
+					args = args[1:]
+				} else if ui12.Imm == 0 && inst.Args[0].(Reg) == R0 && inst.Args[1].(Reg) == R0 {
+					return "NOOP"
+				}
+
+			case SLL_W, OR:
+				rk := inst.Args[2].(Reg)
+				if rk == R0 {
+					args = args[1:]
+					if inst.Op == SLL_W {
+						op = "MOVW"
+					} else {
+						op = "MOVV"
+					}
+				}
+			}
+		}
+	}
+
+	if args != nil {
+		op += " " + strings.Join(args, ", ")
+	}
+	return op
+}
+
+func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
+	// Reg:			gpr[0, 31] and fpr[0, 31]
+	// Fcsr:		fcsr[0, 3]
+	// Fcc:			fcc[0, 7]
+	// Uimm:		unsigned integer constant
+	// Simm16:		si16
+	// Simm32:		si32
+	// OffsetSimm:	si32
+	switch a := arg.(type) {
+	case Reg:
+		regenum := uint16(a)
+		regno := uint16(a) & 0x1f
+		// General-purpose register
+		if regenum >= uint16(R0) && regenum <= uint16(R31) {
+			return fmt.Sprintf("R%d", regno)
+		} else { // Float point register
+			return fmt.Sprintf("F%d", regno)
+		}
+
+	case Fcsr:
+		regno := uint8(a) & 0x1f
+		return fmt.Sprintf("FCSR%d", regno)
+
+	case Fcc:
+		regno := uint8(a) & 0x1f
+		return fmt.Sprintf("FCC%d", regno)
+
+	case Uimm:
+		return fmt.Sprintf("$%d", a.Imm)
+
+	case Simm16:
+		si16 := signumConvInt32(int32(a.Imm), a.Width)
+		return fmt.Sprintf("$%d", si16)
+
+	case Simm32:
+		si32 := signumConvInt32(a.Imm, a.Width)
+		return fmt.Sprintf("$%d", si32)
+
+	case OffsetSimm:
+		offs := offsConvInt32(a.Imm, a.Width)
+		if inst.Op == B || inst.Op == BL {
+			addr := int64(pc) + int64(a.Imm)
+			if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base {
+				return fmt.Sprintf("%s(SB)", s)
+			}
+		}
+		return fmt.Sprintf("%d(PC)", offs>>2)
+
+	case SaSimm:
+		return fmt.Sprintf("$%d", a)
+
+	case CodeSimm:
+		return fmt.Sprintf("$%d", a)
+
+	}
+	return strings.ToUpper(arg.String())
+}
+
+func signumConvInt32(imm int32, width uint8) int32 {
+	active := uint32(1<<width) - 1
+	signum := uint32(imm) & active
+	if ((signum >> (width - 1)) & 0x1) == 1 {
+		signum |= ^active
+	}
+	return int32(signum)
+}
+
+func offsConvInt32(imm int32, width uint8) int32 {
+	relWidth := width + 2
+	return signumConvInt32(imm, relWidth)
+}
+
+var plan9OpMap = map[Op]string{
+	ADD_W:       "ADD",
+	ADD_D:       "ADDV",
+	SUB_W:       "SUB",
+	SUB_D:       "SUBV",
+	ADDI_W:      "ADD",
+	ADDI_D:      "ADDV",
+	LU12I_W:     "LU12IW",
+	LU32I_D:     "LU32ID",
+	LU52I_D:     "LU52ID",
+	SLT:         "SGT",
+	SLTU:        "SGTU",
+	SLTI:        "SGT",
+	SLTUI:       "SGTU",
+	PCADDU12I:   "PCADDU12I",
+	PCALAU12I:   "PCALAU12I",
+	AND:         "AND",
+	OR:          "OR",
+	NOR:         "NOR",
+	XOR:         "XOR",
+	ANDI:        "AND",
+	ORI:         "OR",
+	XORI:        "XOR",
+	MUL_W:       "MUL",
+	MULH_W:      "MULH",
+	MULH_WU:     "MULHU",
+	MUL_D:       "MULV",
+	MULH_D:      "MULHV",
+	MULH_DU:     "MULHVU",
+	DIV_W:       "DIV",
+	DIV_WU:      "DIVU",
+	DIV_D:       "DIVV",
+	DIV_DU:      "DIVVU",
+	MOD_W:       "REM",
+	MOD_WU:      "REMU",
+	MOD_D:       "REMV",
+	MOD_DU:      "REMVU",
+	SLL_W:       "SLL",
+	SRL_W:       "SRL",
+	SRA_W:       "SRA",
+	ROTR_W:      "ROTR",
+	SLL_D:       "SLLV",
+	SRL_D:       "SRLV",
+	SRA_D:       "SRAV",
+	ROTR_D:      "ROTRV",
+	SLLI_W:      "SLL",
+	SRLI_W:      "SRL",
+	SRAI_W:      "SRA",
+	ROTRI_W:     "ROTR",
+	SLLI_D:      "SLLV",
+	SRLI_D:      "SRLV",
+	SRAI_D:      "SRAV",
+	ROTRI_D:     "ROTRV",
+	EXT_W_B:     "?",
+	EXT_W_H:     "?",
+	BITREV_W:    "BITREVW",
+	BITREV_D:    "BITREVV",
+	CLO_W:       "CLOW",
+	CLO_D:       "CLOV",
+	CLZ_W:       "CLZW",
+	CLZ_D:       "CLZV",
+	CTO_W:       "CTOW",
+	CTO_D:       "CTOV",
+	CTZ_W:       "CTZW",
+	CTZ_D:       "CTZV",
+	REVB_2H:     "REVB2H",
+	REVB_2W:     "REVB2W",
+	REVB_4H:     "REVB4H",
+	REVB_D:      "REVBV",
+	BSTRPICK_W:  "BSTRPICKW",
+	BSTRPICK_D:  "BSTRPICKV",
+	BSTRINS_W:   "BSTRINSW",
+	BSTRINS_D:   "BSTRINSV",
+	MASKEQZ:     "MASKEQZ",
+	MASKNEZ:     "MASKNEZ",
+	BCNEZ:       "BFPT",
+	BCEQZ:       "BFPF",
+	BEQ:         "BEQ",
+	BNE:         "BNE",
+	BEQZ:        "BEQ",
+	BNEZ:        "BNE",
+	BLT:         "BLT",
+	BLTU:        "BLTU",
+	BGE:         "BGE",
+	BGEU:        "BGEU",
+	B:           "JMP",
+	BL:          "CALL",
+	LD_B:        "MOVB",
+	LD_H:        "MOVH",
+	LD_W:        "MOVW",
+	LD_D:        "MOVV",
+	LD_BU:       "MOVBU",
+	LD_HU:       "MOVHU",
+	LD_WU:       "MOVWU",
+	ST_B:        "MOVB",
+	ST_H:        "MOVH",
+	ST_W:        "MOVW",
+	ST_D:        "MOVV",
+	LDX_B:       "MOVB",
+	LDX_BU:      "MOVBU",
+	LDX_D:       "MOVV",
+	LDX_H:       "MOVH",
+	LDX_HU:      "MOVHU",
+	LDX_W:       "MOVW",
+	LDX_WU:      "MOVWU",
+	STX_B:       "MOVB",
+	STX_D:       "MOVV",
+	STX_H:       "MOVH",
+	STX_W:       "MOVW",
+	AMADD_B:     "AMADDB",
+	AMADD_D:     "AMADDV",
+	AMADD_DB_B:  "AMADDDBB",
+	AMADD_DB_D:  "AMADDDBV",
+	AMADD_DB_H:  "AMADDDBH",
+	AMADD_DB_W:  "AMADDDBW",
+	AMADD_H:     "AMADDH",
+	AMADD_W:     "AMADDW",
+	AMAND_D:     "AMANDV",
+	AMAND_DB_D:  "AMANDDBV",
+	AMAND_DB_W:  "AMANDDBW",
+	AMAND_W:     "AMANDW",
+	AMCAS_B:     "AMCASB",
+	AMCAS_D:     "AMCASV",
+	AMCAS_DB_B:  "AMCASDBB",
+	AMCAS_DB_D:  "AMCASDBV",
+	AMCAS_DB_H:  "AMCASDBH",
+	AMCAS_DB_W:  "AMCASDBW",
+	AMCAS_H:     "AMCASH",
+	AMCAS_W:     "AMCASW",
+	AMMAX_D:     "AMMAXV",
+	AMMAX_DB_D:  "AMMAXDBV",
+	AMMAX_DB_DU: "AMMAXDBVU",
+	AMMAX_DB_W:  "AMMAXDBW",
+	AMMAX_DB_WU: "AMMAXDBWU",
+	AMMAX_DU:    "AMMAXVU",
+	AMMAX_W:     "AMMAXW",
+	AMMAX_WU:    "AMMAXWU",
+	AMMIN_D:     "AMMINV",
+	AMMIN_DB_D:  "AMMINDBV",
+	AMMIN_DB_DU: "AMMINDBVU",
+	AMMIN_DB_W:  "AMMINDBW",
+	AMMIN_DB_WU: "AMMINDBWU",
+	AMMIN_DU:    "AMMINVU",
+	AMMIN_W:     "AMMINW",
+	AMMIN_WU:    "AMMINWU",
+	AMOR_D:      "AMORV",
+	AMOR_DB_D:   "AMORDBV",
+	AMOR_DB_W:   "AMORDBW",
+	AMOR_W:      "AMORW",
+	AMSWAP_B:    "AMSWAPB",
+	AMSWAP_D:    "AMSWAPV",
+	AMSWAP_DB_B: "AMSWAPDBB",
+	AMSWAP_DB_D: "AMSWAPDBV",
+	AMSWAP_DB_H: "AMSWAPDBH",
+	AMSWAP_DB_W: "AMSWAPDBW",
+	AMSWAP_H:    "AMSWAPH",
+	AMSWAP_W:    "AMSWAPW",
+	AMXOR_D:     "AMXORV",
+	AMXOR_DB_D:  "AMXORDBV",
+	AMXOR_DB_W:  "AMXORDBW",
+	AMXOR_W:     "AMXORW",
+	LL_W:        "LL",
+	LL_D:        "LLV",
+	SC_W:        "SC",
+	SC_D:        "SCV",
+	CRCC_W_B_W:  "CRCCWBW",
+	CRCC_W_D_W:  "CRCCWVW",
+	CRCC_W_H_W:  "CRCCWHW",
+	CRCC_W_W_W:  "CRCCWWW",
+	CRC_W_B_W:   "CRCWBW",
+	CRC_W_D_W:   "CRCWVW",
+	CRC_W_H_W:   "CRCWHW",
+	CRC_W_W_W:   "CRCWWW",
+	DBAR:        "DBAR",
+	SYSCALL:     "SYSCALL",
+	BREAK:       "BREAK",
+	RDTIMEL_W:   "RDTIMELW",
+	RDTIMEH_W:   "RDTIMEHW",
+	RDTIME_D:    "RDTIMED",
+	CPUCFG:      "CPUCFG",
+
+	// Floating-point instructions
+	FADD_S:       "ADDF",
+	FADD_D:       "ADDD",
+	FSUB_S:       "SUBF",
+	FSUB_D:       "SUBD",
+	FMUL_S:       "MULF",
+	FMUL_D:       "MULD",
+	FDIV_S:       "DIVF",
+	FDIV_D:       "DIVD",
+	FMSUB_S:      "FMSUBF",
+	FMSUB_D:      "FMSUBD",
+	FMADD_S:      "FMADDF",
+	FMADD_D:      "FMADDD",
+	FNMADD_S:     "FNMADDF",
+	FNMADD_D:     "FNMADDD",
+	FNMSUB_S:     "FNMSUBF",
+	FNMSUB_D:     "FNMSUBD",
+	FABS_S:       "ABSF",
+	FABS_D:       "ABSD",
+	FNEG_S:       "NEGF",
+	FNEG_D:       "NEGD",
+	FSQRT_S:      "SQRTF",
+	FSQRT_D:      "SQRTD",
+	FCOPYSIGN_S:  "FCOPYSGF",
+	FCOPYSIGN_D:  "FCOPYSGD",
+	FMAX_S:       "FMAXF",
+	FMAX_D:       "FMAXD",
+	FMIN_S:       "FMINF",
+	FMIN_D:       "FMIND",
+	FCLASS_S:     "FCLASSF",
+	FCLASS_D:     "FCLASSD",
+	FCMP_CEQ_S:   "CMPEQF",
+	FCMP_CEQ_D:   "CMPEQD",
+	FCMP_SLE_S:   "CMPGEF",
+	FCMP_SLE_D:   "CMPGED",
+	FCMP_SLT_S:   "CMPGTF",
+	FCMP_SLT_D:   "CMPGTD",
+	FCVT_D_S:     "MOVFD",
+	FCVT_S_D:     "MOVDF",
+	FFINT_S_W:    "FFINTFW",
+	FFINT_S_L:    "FFINTFV",
+	FFINT_D_W:    "FFINTDW",
+	FFINT_D_L:    "FFINTDV",
+	FTINTRM_L_D:  "FTINTRMVD",
+	FTINTRM_L_S:  "FTINTRMVF",
+	FTINTRM_W_D:  "FTINTRMWD",
+	FTINTRM_W_S:  "FTINTRMWF",
+	FTINTRNE_L_D: "FTINTRNEVD",
+	FTINTRNE_L_S: "FTINTRNEVF",
+	FTINTRNE_W_D: "FTINTRNEWD",
+	FTINTRNE_W_S: "FTINTRNEWF",
+	FTINTRP_L_D:  "FTINTRPVD",
+	FTINTRP_L_S:  "FTINTRPVF",
+	FTINTRP_W_D:  "FTINTRPWD",
+	FTINTRP_W_S:  "FTINTRPWF",
+	FTINTRZ_L_D:  "FTINTRZVD",
+	FTINTRZ_L_S:  "FTINTRZVF",
+	FTINTRZ_W_D:  "FTINTRZWD",
+	FTINTRZ_W_S:  "FTINTRZWF",
+	FTINT_L_D:    "FTINTVD",
+	FTINT_L_S:    "FTINTVF",
+	FTINT_W_D:    "FTINTWD",
+	FTINT_W_S:    "FTINTWF",
+	FRINT_S:      "FRINTS",
+	FRINT_D:      "FRINTD",
+	FMOV_S:       "MOVF",
+	FMOV_D:       "MOVD",
+	MOVGR2FR_W:   "MOVW",
+	MOVGR2FR_D:   "MOVV",
+	MOVFR2GR_S:   "MOVW",
+	MOVFR2GR_D:   "MOVV",
+	MOVGR2CF:     "MOVV",
+	MOVCF2GR:     "MOVV",
+	MOVFCSR2GR:   "MOVV",
+	MOVGR2FCSR:   "MOVV",
+	MOVFR2CF:     "MOVV",
+	MOVCF2FR:     "MOVV",
+	FLD_S:        "MOVF",
+	FLD_D:        "MOVD",
+	FST_S:        "MOVF",
+	FST_D:        "MOVD",
+	FLDX_S:       "MOVF",
+	FLDX_D:       "MOVD",
+	FSTX_S:       "MOVF",
+	FSTX_D:       "MOVD",
+}

vendor/modules.txt

@@ -72,9 +72,10 @@ go.starlark.net/resolve
 go.starlark.net/starlark
 go.starlark.net/starlarkstruct
 go.starlark.net/syntax
-# golang.org/x/arch v0.6.0
+# golang.org/x/arch v0.11.0
 ## explicit; go 1.18
 golang.org/x/arch/arm64/arm64asm
+golang.org/x/arch/loong64/loong64asm
 golang.org/x/arch/ppc64/ppc64asm
 golang.org/x/arch/x86/x86asm
 # golang.org/x/exp v0.0.0-20230224173230-c95f2b4c22f2